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order this document by mc68hc16s2ts/d m this document contains information on a new product. specifications and information herein are subject to change without notice. ?motorola inc., 1996 motorola semiconductor technical data mc68hc16s2 technical summary 16-bit modular microcontroller 1 introduction the mc68hc16s2 is a high-speed 16-bit microcontroller. it is a member of the mc68300/m68hc16 family. m68hc16 microcontrollers are built up from standard modules that interface through a common inter- module bus (imb). standardization facilitates rapid development of devices tailored for specific applica- tions. the mcu incorporates a 16-bit central processing unit (cpu16), a system integration module (sim), and a 2-kbyte standby ram module (sram). the mcu clock can either be synthesized from an external reference or input directly. operation with a 32.768 khz reference frequency is standard. the maximum system clock speed is 25.17 mhz. system hardware and software allow changes in clock rate during operation. because mcu operation is fully static, register and memory contents are not affected by clock rate changes. high-density complementary metal-oxide semiconductor (hcmos) architecture makes the basic power consumption of the mcu low. power consumption can be minimized by stopping the system clock. the m68hc16 instruction set includes a low-power stop (lpstop) command that efficiently implements this capability. table 1 mc68hc16s2 ordering information package type frequency (mhz) temperature package order quantity order number 100-pin tqfp 20.97 mhz ?40 to + 85 c 2 spmc16s2cpu20 84 mc68hc16s2cpu20 420 MC16S2CPU20B1 25.17 mhz ?40 to + 85 c 2 spmc16s2cpu25 84 mc68hc16s2cpu25 420 mc16s2cpu25b1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section page motorola mc68hc16s2 2 mc68hc16s2ts/d 1 introduction 1 1.1 features ...................................................................................................................................... 3 1.2 block diagram ............................................................................................................................. 4 1.3 pin assignments .......................................................................................................................... 5 1.4 address map ............................................................................................................................... 6 1.5 intermodule bus .......................................................................................................................... 6 2 signal descriptions 7 2.1 pin characteristics ...................................................................................................................... 7 2.2 power connections ..................................................................................................................... 8 2.3 output driver types .................................................................................................................... 8 2.4 signal characteristics .................................................................................................................. 8 2.5 signal functions .......................................................................................................................... 9 3 system integration module 10 3.1 overview ................................................................................................................................... 10 3.2 system configuration block ...................................................................................................... 12 3.3 system clock ............................................................................................................................ 14 3.4 system protection block ........................................................................................................... 19 3.5 external bus interface ............................................................................................................... 24 3.6 chip-selects .............................................................................................................................. 28 3.7 general-purpose input/output .................................................................................................. 37 3.8 resets ....................................................................................................................................... 39 3.9 interrupts ................................................................................................................................... 42 3.10 factory test block ..................................................................................................................... 44 4 central processing unit 45 4.1 overview ................................................................................................................................... 45 4.2 m68hc11 compatibility ............................................................................................................. 45 4.3 programming model .................................................................................................................. 46 4.4 data types ................................................................................................................................ 47 4.5 addressing modes ..................................................................................................................... 48 4.6 instruction set ........................................................................................................................... 49 4.7 exceptions ................................................................................................................................. 68 5 standby ram module 71 5.1 overview ................................................................................................................................... 71 5.2 sram register block ................................................................................................................ 71 5.3 sram registers ........................................................................................................................ 71 5.4 sram operation ....................................................................................................................... 73 6 electrical characteristics 74 table of contents f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 3 1.1 features ?cpu16 ?16-bit architecture ?full set of 16-bit instructions ?three 16-bit index registers ?two 16-bit accumulators ?control-oriented digital signal processing capability ?one mbyte of program memory and one mbyte of data memory ?high-level language support ?fast interrupt response time ?background debugging mode ?fully static operation ?system integration module (sim) ?external bus support ?programmable chip select outputs ?system protection logic ?watchdog timer, clock monitor and bus monitor ?two 8-bit dual function input/output ports ?one 7-bit dual function output port ?phase-locked loop (pll) clock system ?standby ram module (sram) ?2 kbytes of static ram ?external standby voltage supply input f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 4 mc68hc16s2ts/d 1.2 block diagram figure 1 mc68hc16s2 block diagram csboot siz1 siz0 as ds pe3 siz1/pe7 siz0/pe6 as /pe5 ds /pe4 avec /pe2 dsack1 /pe1 dsack0 /pe0 addr22/cs9 /pc6 addr21/cs8 /pc5 addr20/cs7 /pc4 br bg r/w reset halt berr data[15:0] addr[23:19] test ebi control addr19/cs6 /pc3 fc2/cs5 /pc2 fc1/cs4 /pc1 fc0/cs3 /pc0 addr23/cs10 cs[10:0] control port e fc2 fc1 fc0 chip select clock bgack avec dsack1 dsack0 port f control irq6 /pf6 modclk/pf0 irq7 /pf7 irq5 /pf5 irq4 /pf4 irq3 /pf3 irq2 /pf2 irq1 /pf1 tsc quot tsc freeze/quot freeze cpu16 sim extal xfc v ddsyn xtal clkout modclk addr[18:0] control port c imb irq[7:1] s2block bgack /cs2 bg /cs1 br /cs0 2k sram control pe3 dsclk dso dsi ipipe0 ipipe1 bkpt bkpt /dsclk ipipe1/dsi ipipe0/dso v stby v dd (10) v ss (12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 5 1.3 pin assignments figure 2 mc68hc16s2 pin assignments data10 data11 data12 data13 vsse vdde data14 data15 addr0 dsack0 /pe0 dsack1 /pe1 avec /pe2 vssi pe3 ds /pe4 as /pe5 siz0/pe6 siz1/pe7 vsse5 vdde5 r/w modclk/pf0 irq1 /pf1 irq2 /pf2 irq3 /pf3 addr20/cs7 /pc4 addr19/cs6 /pc3 fc2/cs5 /pc2 fc1/cs4 /pc1 vsse vdde fc0/cs3 /pc0 bgack /cs2 bg /cs1 br /cs0 csboot vssi vddi data0 data1 data2 data3 data4 vsse vdde data5 data6 data7 data8 data9 adr21/cs8 /pc5 addr22/cs9 /pc6 addr23/cs10 /eclk bkpt /dsclk vdde vsse ipipe0/dso ipipe1/dsi addr1 addr2 addr3 addr4 vssi addr5 addr6 addr7 addr8 addr9 vdde vsse addr10 addr11 addr12 addr13 addr14 addr15 addr16 addr17 addr18 vsse clkout vdde xfc vddi vssi extal vddsyn xtal vstby freeze/quot tsc reset halt vdde vsse berr irq7 /pf7 irq6 /pf6 irq5 /pf5 irq4 /pf4 mc68hc16s2 16s2 100-pin qfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 6 mc68hc16s2ts/d 1.4 address map figure 3 is a map of the mcu internal addresses. although there are 24 intermodule bus (imb) address lines, the cpu16 uses only addr[19:0]. addr[23:20] follow the logic state of addr19. addresses $080000 to $f7ffff are not accessible. the ram array is positioned by the base address register in the associated ram control block. unimplemented blocks are mapped externally. figure 3 mc68hc16s2 address map 1.5 intermodule bus the intermodule bus (imb) is a standardized bus developed to facilitate both design and operation of modular microcontrollers. it contains circuitry to support exception processing, address space partition- ing, multiple interrupt levels, and vectored interrupts. the standardized modules in the mc68hc16s2 communicate with one another and with external components through the imb. although the full imb supports 24 address and 16 data lines, the mc68hc16s2 uses only 16 data lines and 20 address lines. because the cpu16 uses only 20 address lines, addr[23:20] follow the state of addr19. $yffa00 $yffa7f $yffb00 $yffb07 $000000 $ffffff base address sram array 2048 bytes sim 128 bytes sram ctl 16s2 address map 8 bytes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 7 2 signal descriptions 2.1 pin characteristics table 2 shows mcu pins and their characteristics. all inputs detect cmos logic levels. all inputs can be put in a high impedance state, but the method of doing this differs depending upon pin function. refer to table 4 for a description of output drivers. an entry in the discrete i/o column of the mcu pin char- acteristics table indicates that a pin has an alternate i/o function. the port designation is given when it applies. refer to the mcu block diagram for information about port organization. notes: 1. hal t and berr synchronized only if late hal t or berr . 2. data[15:0] are synchronized during reset only. modclk is synchronized only when used as a port i/o pin. table 2 mcu pin characteristics pin mnemonic output driver input synchronized input hysteresis discrete i/o port designation addr23/cs10 /eclk a yes no addr[22:19]/cs[9: 6] a yes no o pc[6:3] addr[18:0] a yes no as b yes no i/o pe5 a vec b yes no i/o pe2 berr b yes 1 no bg /cs1 b bga ck /cs2 b yes no bkpt /dsclk yes yes br /cs0 b yes no clkout a csboo t b data[15:0] aw yes 2 no ds b yes no i/o pe4 dsa ck[1:0] b yes no i/o pe[1:0] extal yes fc[2:0]/cs[5:3] a yes no o pc[2:0] freeze/quot a hal t bo yes 1 no ipipe0/dso a ipipe1/dsi a yes yes irq[7:1] b yes yes i/o pf[7:1] modclk 2 b yes no i/o pf0 r/w a yes no reset bo yes yes pe3 b yes yes i/o pe3 siz[1:0] b yes no i/o pe[7:6] tsc yes yes xfc xtal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 8 mc68hc16s2ts/d 2.2 power connections 2.3 output driver types 2.4 signal characteristics table 3 mcu power connections pin description v stby standby ram power v ddsyn clock synthesizer power v sse v dde external periphery output driver power (source and drain) v ssi, v ddi internal module power (source and drain) table 4 mcu output driver types type i/o description a o output only signals that are always driven; no external pull-up required aw o type a output with weak p-channel pull-up during reset b o three-state output that includes circuitry to pull up output before high impedance is established to ensure rapid rise time. an external holding resistor is required to maintain logic level while the pin is in the high-impedance state. bo o type b output that can be operated in an open-drain mode. table 5 mcu signal characteristics signal name mcu module signal type active state addr[23:0] sim bus as sim output 0 a vec sim input 0 berr sim input 0 bg sim output 0 bga ck sim input 0 bkpt cpu16 input 0 br sim input 0 clkout sim output cs[10:0] sim output 0 csboo t sim output 0 data[15:0] sim bus ds sim output 0 dsa ck[1:0] sim input 0 dsclk cpu16 input dsi cpu16 input dso cpu16 output extal sim input fc[2:0] sim output freeze sim output 1 hal t sim input/output 0 ipipe[1:0] cpu16 output irq[7:1] sim input 0 modclk sim input f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 9 2.5 signal functions quot sim output r/w sim output 1/0 reset sim input/output 0 pe3 sim output siz[1:0] sim output tsc sim input xfc sim input xtal sim output table 6 mcu signal functions signal name mnemonic function address bus addr[23:0] 20-bit address bus used by cpu16; addr[23:20] follow addr19 address strobe as indicates that a valid address is on the address bus autovector a vec requests an automatic vector during interrupt acknowledge bus error berr signals a bus error to the cpu bus grant bg indicates that the mcu has relinquished the bus bus grant acknowledge bga ck indicates that an external device has assumed bus mastership breakpoint bkpt signals a hardware breakpoint to the cpu bus request br indicates that an external device requires bus mastership system clock out clkout system clock output chip selects cs[10:0] select external devices at programmed addresses boot chip select csboo t chip-select for external boot start-up rom data bus data[15:0] 16-bit data bus data strobe ds indicates that an external device should place valid data on the data bus during a read cycle and that valid data has been placed on the bus by the cpu during a write cycle data and size acknowledge dsa ck[1:0] acknowledges to the sim that data has been received for a write cycle, or that data is valid on the data bus for a read cycle development serial in, out, clock dsi, dso,dsclk serial i/o and clock for background debug mode crystal oscillator extal, xtal connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used function codes fc[2:0] identify processor state and current address space freeze freeze indicates that the cpu has entered background debug mode halt hal t suspend external bus activity instruction pipeline ipipe[1:0] indicate instruction pipeline activity interrupt request level irq[7:1] request interrupt service from the cpu clock mode select modclk selects system clock source quotient out quot provides the quotient bit of the polynomial divider reset reset system reset read/write r/w indicates the direction of data transfer on the bus size siz[1:0] indicates the number of bytes to be transferred during a bus cycle three-state control tsc places all output drivers in a high impedance state external filter capacitor xfc connection for external phase-locked loop filter capacitor table 5 mcu signal characteristics (continued) signal name mcu module signal type active state f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 10 mc68hc16s2ts/d 3 system integration module the system integration module (sim) consists of six functional blocks that control system startup, ini- tialization, configuration, and external bus. figure 4 shows the sim block diagram. figure 4 sim block diagram 3.1 overview the system configuration block controls mcu configuration and operating mode. the clock synthesizer generates clock signals used by the sim, other imb modules, and external de- vices. in addition, a periodic interrupt generator supports execution of time-critical control routines. the system protection block provides bus and software watchdog monitors. the chip-select block provides eleven general-purpose chip-select signals and a boot rom chip-select signal. both general-purpose and boot rom chip-select signals have associated base address regis- ters and option registers. the external bus interface handles the transfer of information between imb modules and external ad- dress space. the system test block incorporates hardware necessary for testing the mcu. it is used to perform fac- tory tests, and its use in normal applications is not supported. table 7 shows the sim address map, which occupies 128 bytes. unused registers within the 128-byte address space return zeros when read. s(c)im block system configuration clock synthesizer chip-selects external bus interface factory test clkout extal modclk chip-selects external bus reset tsc freeze/quot xtal system protection f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 11 table 7 sim address map address 15 8 7 0 $yffa00 1 sim module configuration register (simcr) $yffa02 sim test register (simtr) $yffa04 clock synthesizer control register (syncr) $yffa06 not used reset status register (rsr) $yffa08 sim test register e (simtre) $yffa0a not used $yffa0c not used $yffa0e not used $yffa10 not used port e data (porte0) $yffa12 not used port e data (porte1) $yffa14 not used port e data direction (ddre) $yffa16 not used port e pin assignment (pepar) $yffa18 not used port f data (portf0) $yffa1a not used port f data (portf1) $yffa1c not used port f data direction (ddrf) $yffa1e not used port f pin assignment (pfpar) $yffa20 not used system protection control (sypcr) $yffa22 periodic interrupt control register (picr) $yffa24 periodic interrupt timer register (pitr) $yffa26 not used software service (swsr) $yffa28 not used $yffa2a not used $yffa2c not used $yffa2e not used $yffa30 test module master shift a (tstmsra) $yffa32 test module master shift b (tstmsrb) $yffa34 test module shift count (tstsc) $yffa36 test module repetition counter (tstrc) $yffa38 test module control (creg) $yffa3a test module distributed register (dreg) $yffa3c not used $yffa3e not used $yffa40 not used port c data (portc) $yffa42 not used $yffa44 chip-select pin assignment (cspar0) $yffa46 chip-select pin assignment (cspar1) $yffa48 chip-select base boot (csbarbt) $yffa4a chip-select option boot (csorbt) $yffa4c chip-select base 0 (csbar0) $yffa4e chip-select option 0 (csor0) $yffa50 chip-select base 1 (csbar1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 12 mc68hc16s2ts/d 3.2 system configuration block the sim controls mcu configuration during normal operation and during internal testing. the sim configuration register controls system configuration. it can be read or written at any time, ex- cept for the module mapping (mm) bit, which can be written only once. exoff ?external clock off 0 = the clkout pin is driven by the mcu system clock. 1 = the clkout pin is placed in a high-impedance state. notes: 1. y = m111, where m is the logic state of the module mapping (mm) bit in the simcr. $yffa52 chip-select option 1 (csor1) $yffa54 chip-select base 2 (csbar2) $yffa56 chip-select option 2 (csor2) $yffa58 chip-select base 3 (csbar3) $yffa5a chip-select option 3 (csor3) $yffa5c chip-select base 4 (csbar4) $yffa5e chip-select option 4 (csor4) $yffa60 chip-select base 5 (csbar5) $yffa62 chip-select option 5 (csor5) $yffa64 chip-select base 6 (csbar6) $yffa66 chip-select option 6 (csor6) $yffa68 chip-select base 7 (csbar7) $yffa6a chip-select option 7 (csor7) $yffa6c chip-select base 8 (csbar8) $yffa6e chip-select option 8 (csor8) $yffa70 chip-select base 9 (csbar9) $yffa72 chip-select option 9 (csor9) $yffa74 chip-select base 10 (csbar10) $yffa76 chip-select option 10 (csor10) $yffa78 not used $yffa7a not used $yffa7c not used $yffa7e not used simcr sim configuration register $yffa00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 exoff frzsw frzbm 0 slven 0 shen supv mm 0 0 iarb[3:0] reset: 0 0 0 0 data11 0 0 0 1 1 0 0 1 1 1 1 table 7 sim address map (continued) address 15 8 7 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 13 frzsw ?freeze software enable 0 = when freeze is asserted, the software watchdog and periodic interrupt timer counters con- tinue to run. 1 = when freeze is asserted, the software watchdog and periodic interrupt timer counters are dis- abled, preventing interrupts while the mcu is in background debug mode. frzbm ?freeze bus monitor enable 0 = when freeze is asserted, the bus monitor continues to operate. 1 = when freeze is asserted, the bus monitor is disabled. slven ?factory test mode enabled this bit is a read-only status bit that reflects the state of data11 during reset. 0 = imb is not available to an external master. 1 = an external bus master has direct access to the imb. shen[1:0] ?show cycle enable this field determines what the ebi does with the external bus during internal transfer operations. a show cycle allows internal transfers to be externally monitored. table 8 shows whether show cycle data is driven externally, and whether external bus arbitration can occur. to prevent bus conflict, external peripherals must not be enabled during show cycles. supv ?supervisor/unrestricted data space this bit has no effect because the cpu16 always operates in the supervisor mode. mm ?module mapping 0 = internal modules are addressed from $7ff000 ?$7fffff. 1 = internal modules are addressed from $fff000 ?$ffffff. the logic state of mm determines the value of addr23 for imb module addresses. because addr[23:20] are driven to the same state as addr19, mm must be set to one. if mm is cleared, imb modules are inaccessible. this bit can be written only once after reset. iarb[3:0] ?interrupt arbitration field each module that can generate interrupt requests has an interrupt arbitration (iarb) field. arbitration between interrupt requests of the same priority is performed by serial contention between iarb field bit values. contention must take place whenever an interrupt request is acknowledged, even when there is only a single pending request. an iarb field must have a non-zero value for contention to take place. if an interrupt request from a module with an iarb field value of %0000 is recognized, the cpu pro- cesses a spurious interrupt exception. because the sim routes external interrupt requests to the cpu, the sim iarb field value is used for arbitration between internal and external interrupts of the same pri- ority. the reset value of iarb for the sim is %1111, and the reset value of iarb for all other modules is %0000, which prevents sim interrupts from being discarded during initialization. table 8 show cycle enable bits shen[1:0] action 00 show cycles disabled, external bus arbitration allowed 01 show cycles enabled, external bus arbitration not allowed 10 show cycles enabled, external bus arbitration allowed 11 show cycles enabled, external bus arbitration allowed, internal activity is halted by a bus grant f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 14 mc68hc16s2ts/d 3.3 system clock the system clock in the sim provides timing signals for the imb modules and for an external peripheral bus. because the mcu is a fully static design, register and memory contents are not affected when the clock rate changes. system hardware and software support changes in clock rate during operation. the system clock signal can be generated in one of two ways. an internal phase-locked loop can syn- thesize the clock from a reference frequency, or the clock signal can be input directly from an external source. keep these clock sources in mind while reading the rest of this section. figure 5 is a block diagram of the system clock. figure 5 system clock block diagram 3.3.1 clock sources the state of the modclk pin during reset determines the system clock source. when modclk is held high during reset, the clock synthesizer generates a clock signal from a reference frequency connected to the extal pin. the clock synthesizer control register (syncr) determines operating frequency and mode of operation. when modclk is held low during reset, the clock synthesizer is disabled and an external system clock signal must be applied. the syncr control bits have no effect. the input clock is referred to as ? ref ? and can be either a crystal or an external clock source. the output of the clock system is referred to as ? sys ? ensure that f ref and f sys are within normal operating limits. the reference frequency for this mcu is typically 32.768 khz, but can range from 25 khz to 50 khz. to generate a reference frequency using the crystal oscillator, a reference crystal must be connected be- tween the extal and xtal pins. figure 6 shows a recommended circuit. 32 pll block phase comparator low-pass filter vco crystal oscillator system clock system clock control feedback divider w x y extal xtal xfc v ddsyn clkout f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 15 figure 6 system clock oscillator circuit when an external system clock signal is applied (pll disabled, modclk = 0 during reset), the duty cycle of the input is critical, especially at operating frequencies close to maximum. the relationship be- tween clock signal duty cycle and clock signal period is expressed: when the system clock signal is applied directly to the extal pin (pll is disabled, modclk = 0 during reset), or the clock synthesizer reference frequency is supplied by a source other than a crystal (pll enabled, modclk = 1 during reset), the xtal pin must be left floating. in either case, the frequency of the signal applied to extal may not exceed the maximum system clock frequency (pll disabled) or the maximum clock synthesizer reference frequency (pll enabled). 3.3.2 clock synthesizer operation v ddsyn is used to power the clock circuits when the phase-locked loop is used. a separate power source increases mcu noise immunity and can be used to run the clock when the mcu is powered down. a quiet power supply must be used as the v ddsyn source. adequate external bypass capacitors should be placed as close as possible to the v ddsyn pin to assure stable operating frequency. when an external system clock signal is applied and the pll is disabled, v ddsyn should be connected to the v dd supply. refer to the sim reference manual (simrm/ad) for more information regarding system clock power supply conditioning. a voltage controlled oscillator (vco) generates the system clock signal. to maintain a 50% clock duty cycle, the vco frequency (f vco ) is either two or four times the system clock frequency, depending on the state of the x bit in syncr. a portion of the clock signal is fed back to a divider/counter. the divider controls the frequency of one input to a phase comparator. the other phase comparator input is the reference signal connected to the extal pin. the comparator generates a control signal proportional to the difference in phase between the two inputs. the signal is low-pass filtered and used to correct the vco output frequency. filter circuit implementation can vary, depending upon the external environment and required clock sta- bility. figure 7 shows a recommended system clock filter network. xfc pin leakage must be kept within specified limits to maintain optimum stability and pll performance. an external filter network connected to the xfc pin is not required when an external system clock signal is applied and the pll is disabled. the xfc pin must be left floating in this case. 32 oscillator extal xtal 10 m w 330 k w 22 pf* 22 pf* v ssi resistance and capacitance based on a test circuit constructed with a daishinku dmx-38 32.768 khz crystal. specific components must be based on crystal type. contact crystal vendor for exact circuit. * r1 c1 c2 r2 minimum external clock period minimum external clock high/low time 50 % percentage variation of external clock input duty cycle ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 16 mc68hc16s2ts/d figure 7 system clock filter network when the clock synthesizer is used, syncr determines the operating frequency of the mcu. the fol- lowing equation relates the mcu operating frequency to the clock synthesizer reference frequency (f ref ) and the w, x, and y fields in syncr: the w bit controls a prescaler tap in the feedback divider. setting w increases vco speed by a factor of four. the y field determines the count modulus for a modulo 64 downcounter, causing it to divide by a value of y+1. when w or y changes, vco frequency (f vco ) changes, and the vco must relock. the x bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. when x=0 (reset state), the divider is enabled, and the system clock is one-fourth the vco frequency. setting x=1 disables the divider, doubling the clock speed without changing the vco frequency. there is no relock delay when clock speed is changed by the x bit. internal vco frequency is determined by the following equations: or for the mcu to operate correctly, system clock and vco frequencies selected by the w, x, and y bits must be within the limits specified for the mcu. do not use a combination of bit values that selects either an operating frequency or a vco frequency greater than the maximum specified values. 3.3.3 clock synthesizer control the clock synthesizer control circuits determine system clock frequency and clock operation under spe- cial circumstances, such as following loss of synthesizer reference or during low-power operation. clock source is determined by the logic state of the modclk pin during reset. notes: 1. ensure that initialization software does not change the value of this bit (it should always be zero). syncr clock synthesizer control register $yffa04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w x y ediv 0 0 rsvd 1 slock rsvd 1 stsim stext reset: 0 0 1 1 1 1 1 1 0 0 0 0 u 0 0 0 32 xfc conn * maintain low leakage on the xfc node. 0.01 m f 0.1 m f xfc * 0.1 m f c4 c3 c1 v ddsyn v ddsyn v ssi f sys 4f ref y1 + () 2 2w x + () = f vco 4f sys if x = 0 = f vco 2f sys if x = 1 = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 17 when the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper byte of syncr. bits in the lower byte show the status of or control the operation of internal and external clocks. syncr can be read or written only when the cpu is operating in supervisor mode. w ?frequency control (vco) this bit controls a prescaler tap in the synthesizer feedback loop. setting it increases the vco speed by a factor of four. vco relock delay is required. x ?frequency control (prescaler) this bit controls a divide by two prescaler that is not in the synthesizer feedback loop. setting it doubles the clock speed without changing the vco speed. no vco relock delay is required. y[5:0] ?frequency control (counter) the y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by a value of y + 1. values range from zero to 63. vco relock delay is required. ediv ?e clock divide rate 0 = eclk frequency is system clock divided by eight. 1 = eclk frequency is system clock divided by 16. eclk is an external m6800 bus clock available on pin addr23. refer to 3.6 chip-selects for more information. slock ?synthesizer lock flag 0 = vco has not locked, but is enabled on the desired frequency. 1 = vco has locked on the desired frequency, or is disabled. the mcu remains in reset until the synthesizer locks, but slock does not indicate synthesizer lock status until after the user writes to syncr. stsim ?stop mode sim clock 0 = when lpstop is executed, the sim clock is driven by the crystal oscillator and the vco is turned off to conserve power. 1 = when lpstop is executed, the sim clock is driven by the vco. stext ?stop mode external clock 0 = when lpstop is executed, the clkout signal is held negated to conserve power. 1 = when lpstop is executed, the clkout signal is driven by the sim clock, as determined by the state of the stsim bit. 3.3.4 external mc6800 bus clock the state of the eclk division rate bit (ediv) in syncr determines clock rate for the eclk signal avail- able on pin addr23. eclk is a bus clock for mc6800 devices and peripherals. eclk frequency can be set to system clock frequency divided by eight or system clock frequency divided by sixteen. the clock is enabled by the cs10 field in chip-select pin assignment register 1 (cspar1). eclk operation during low-power stop is described in the following paragraph. refer to 3.6 chip-selects for more in- formation about the external bus clock. 3.3.5 low-power operation low-power operation is initiated by the cpu16. to reduce power consumption selectively, the cpu16 can enter the following low-power modes: 1. the cpu16 can selectively disable a module by setting the module? stop bit. 2. the cpu16 can execute the lpstop instruction to stop the operations of the entire mcu. if the stop bit in a module is set, then that module enters a low power mode. some or all of that mod- ule? registers remain accessible. the module can be restarted by asserting reset or by the cpu16 clearing the module? stop bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 18 mc68hc16s2ts/d 3.3.5.1 lpstop mode this low power mode offers the greatest power reduction. to enter normal lpstop mode, the cpu16 executes the lpstop instruction after clearing the stcpu bit in syncr. this causes the sim to turn off the system clock to most of the mcu. when the cpu executes lpstop, a special cpu space bus cycle writes a copy of the current interrupt mask into the clock control logic. the sim brings the mcu out of normal lpstop mode when one of the following exceptions occurs: ?reset ?trace ?sim interrupt of higher priority than the stored interrupt mask during lpstop, unless the system clock signal is supplied by an external source and that source is removed, the sim clock control logic and the sim clock signal (simclk) continue to operate. the peri- odic interrupt timer and input logic for the reset and irq pins are clocked by simclk, and can be used to bring the processor out of lpstop. the software watchdog monitor cannot perform this func- tion. optionally, the sim can also continue to generate the clkout signal while in lpstop. stsim and stext bits in syncr determine clock operation during lpstop. the flow chart shown in figure 8 summarizes the effects of the stsim and stext bits when the mcu enters normal lpstop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 19 figure 8 lpstop flowchart 3.4 system protection block system protection includes a bus monitor, a halt monitor, a spurious interrupt monitor, and a software watchdog timer. these functions reduce the number of external components required for complete sys- tem control. figure 9 shows the system protection block. using external clock? no yes use system clock as simclk in lpstop? no yes set stsim = 1 f simclk 1 = f sys in lpstop want clkout on in lpstop? no yes no yes want clkout on in lpstop? set stsim = 0 f simclk 1 = f ref in lpstop set stext = 1 f clkout 2 = f sys f eclk = ? f sys in lpstop set stext = 0 f clkout 2 = 0 hz f eclk = 0 hz in lpstop set stext = 1 f clkout 2 = f ref f eclk = 0 hz in lpstop set stext = 0 f clkout 2 = 0 hz f eclk = 0 hz in lpstop enter lpstop notes: 1. the simclk is used by the pit, irq , and input blocks of the sim. 2. clkout control during lpstop is overridden by the exoff bit in simcr. if exoff = 1, the clkout pin is always in a high impedance state and stext has no effect in lpstop. if exoff = 0, clkout is controlled by stext in lpstop. setup interrupt to wake up mcu from lpstop lpstopflow f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 20 mc68hc16s2ts/d figure 9 system protection block 3.4.1 system protection control register the system protection control register controls the software watchdog timer, bus monitor, and halt monitor. this register can be written only once following power-on or reset, but can be read at any time. swe ?software watchdog enable 0 = software watchdog disabled 1 = software watchdog enabled swp ?software watchdog prescaler this bit controls the value of the software watchdog prescaler. 0 = software watchdog clock not prescaled 1 = software watchdog clock prescaled by 512 sypcr system protection control register $yffa21 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used swe swp swt[1:0] hme bme bmt reset: 1 modclk 0 0 0 0 0 0 sys protect block module configuration and test reset status halt monitor bus monitor spurious interrupt monitor software watchdog timer periodic interrupt timer 2 9 prescaler clock irq[7:1] berr reset request reset request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 21 swt[1:0] ?software watchdog timing this field selects the divide ratio used to establish software watchdog time-out period. table 9 gives the ratio for each combination of swp and swt bits. hme ?halt monitor enable 0 = disable halt monitor function 1 = enable halt monitor function bme ?bus monitor enable 0 = disable bus monitor function for internal to external bus cycles. 1 = enable bus monitor function for internal to external bus cycles. bmt[1:0] ?bus monitor timing this bit field selects the time-out period in system clocks for the bus monitor. refer to table 10 . 3.4.2 bus monitor the internal bus monitor checks for excessively long dsa ck response times during normal bus cycles and for excessively long dsa ck or a vec response times during interrupt acknowledge (iack) cycles. the monitor asserts berr if the response time exceeds a user-specified timeout period. dsa ck and a vec response times are measured in clock cycles. the maximum allowable response time can be selected by setting the bmt[1:0] field. the monitor does not check dsa ck response on the external bus unless the cpu initiates the bus cy- cle. the bme bit in sypcr enables the internal bus monitor for internal to external bus cycles. if a sys- tem contains external bus masters, an external bus monitor must be implemented and the internal to external bus monitor option must be disabled. table 9 software watchdog timing field swp swt[1:0] ratio 000 2 9 001 2 11 010 2 13 011 2 15 100 2 18 101 2 20 110 2 22 111 2 24 table 10 bus monitor time-out period bmt[1:0] bus monitor time-out period 00 64 system clocks 01 32 system clocks 10 16 system clocks 11 8 system clocks f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 22 mc68hc16s2ts/d 3.4.3 halt monitor the halt monitor responds to assertion of the hal t signal on the internal bus caused by a double bus fault. a double bus fault occurs when: ?bus error exception processing begins and a second berr is detected before the first instruction of the first exception handler is executed. ?one or more bus errors occur before the first instruction after a reset exception is executed. ?a bus error occurs while the cpu is loading information from a bus error stack frame during a re- turn from exception (rte) instruction. if the halt monitor is enabled by setting hme in sypcr, the mcu will issue a reset when a double bus fault occurs, otherwise the mcu will remain halted. a flag in the reset status register (rsr) indicates that the last reset was caused by the halt monitor. 3.4.4 spurious interrupt monitor the spurious interrupt monitor issues berr if no interrupt arbitration occurs during an interrupt ac- knowledge cycle. leaving iarb[3:0] set to %0000 in the module configuration register of any peripheral that can generate interrupts will cause a spurious interrupt. 3.4.5 software watchdog the software watchdog is controlled by swe in sypcr. once enabled, the watchdog requires that a service sequence be written to swsr on a periodic basis. if servicing does not take place, the watchdog times out and issues a reset. this register can be written at any time, but returns zeros when read. each time the service sequence is written, the software watchdog timer restarts. the servicing se- quence consists of the following steps: 1. write $55 to swsr. 2. write $aa to swsr. both writes must occur before time-out in the order listed, but any number of instructions can be exe- cuted between the two writes. the watchdog clock rate is affected by swp and swt[1:0] in sypcr. when swt[1:0] are modified, a watchdog service sequence must be performed before the new time-out period takes effect. the reset value of swp is affected by the state of the modclk pin on the rising edge of reset , as shown in table 11 . swsr software service register $yffa27 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used swsr reset: 0 0 0 0 0 0 0 0 table 11 modclk pin states modclk swp 01 10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 23 3.4.6 periodic interrupt timer the periodic interrupt timer (pit) generates interrupts at user-programmable intervals. timing for the pit is provided by a programmable prescaler driven by the system clock. this register contains information concerning periodic interrupt priority and vectoring. bits [10:0] can be read or written at any time. bits [15:11] are unimplemented and always return zero. pirql[2:0] ?periodic interrupt request level table 12 shows what interrupt request level is asserted when a periodic interrupt is generated. if a pit interrupt and an external irq signal of the same priority occur simultaneously, the pit interrupt is ser- viced first. the periodic timer continues to run when the interrupt is disabled. piv[7:0] ?periodic interrupt vector this bit field contains the vector generated in response to an interrupt from the periodic timer. when the sim responds, the periodic interrupt vector is placed on the bus. pitr contains the count value for the periodic timer. setting the pitm[7:0] field turns off the periodic timer. this register can be read or written at any time. ptp ?periodic timer prescaler control 0 = periodic timer clock not prescaled 1 = periodic timer clock prescaled by 512 the reset state of ptp is the complement of the state of the modclk signal at the rising edge of re set . picr periodic interrupt control register $yffa22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 pirql[2:0] piv[7:0] reset: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 table 12 periodic interrupt request levels pirql[2:0] interrupt request level 000 periodic interrupt disabled 001 interrupt request level 1 010 interrupt request level 2 011 interrupt request level 3 100 interrupt request level 4 101 interrupt request level 5 110 interrupt request level 6 111 interrupt request level 7 pitr periodic interrupt timer register $yffa24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ptp pitm[7:0] reset: 0 0 0 0 0 0 0 modclk 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 24 mc68hc16s2ts/d pitm[7:0] ?periodic interrupt timer modulus this is an 8-bit timing modulus. the period of the timer can be calculated as follows: where pit period = periodic interrupt timer period pitm[7:0] = periodic interrupt timer modulus f ref = synthesizer reference of external clock input frequency prescaler = 1 if ptp = 0 or 512 if ptp = 1 3.5 external bus interface the external bus interface (ebi) transfers information between the internal mcu bus and external de- vices. the external bus has 24 address lines and 16 data lines. because the cpu16 in the mc68hc16s2 drives only 20 of the 24 imb address lines, addr[23:20] follow the output state of addr19. the ebi provides dynamic sizing between 8-bit and 16-bit data accesses. it supports byte, word, and long-word transfers. ports are accessed through the use of asynchronous cycles controlled by the size (siz1 and siz0) and data size acknowledge (dsa ck1 and dsa ck0 ) pins. multiple bus cycles may be required for dynamically sized transfer. port width is the maximum number of bits accepted or provided during a bus transfer. external devices must follow the handshake protocol described below. control signals indicate the beginning of the cycle, the address space, the size of the transfer, and the type of cycle. the selected device controls the length of the cycle. strobe signals, one for the address bus and another for the data bus, indicate the validity of an address and provide timing information for data. the ebi operates in an asynchronous mode for any port width. to add flexibility and minimize the necessity for external logic, mcu chip-select logic can be synchro- nized with ebi transfers. chip-select logic can also provide internally-generated bus control signals for these accesses. refer to 3.6 chip-selects for more information. 3.5.1 bus control signals the cpu initiates a bus cycle by driving the address, size, function code, and read/write outputs. at the beginning of the cycle, size signals siz0 and siz1 are driven along with the function code signals fc[2:0]. the size signals indicate the number of bytes remaining to be transferred during an operand cycle. they are valid while the address strobe as is asserted. table 13 shows siz0 and siz1 encoding. the read/write (r/w ) signal determines the direction of the transfer during a bus cycle. this signal changes state, when required, at the beginning of a bus cycle, and is valid while as is asserted. the r/w signal only changes state when a write cycle is preceded by a read cycle or vice versa. the signal can remain low for two consecutive write cycles. table 13 size signal encoding siz1 siz0 transfer size 0 1 byte 1 0 word 1 1 three byte 0 0 long word pit period 4 pitm[7:0] () prescaler () f ref ---------------------------------------------------------------- - = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 25 3.5.2 function codes function code signals fc[2:0] are automatically generated by the cpu16. the function codes can be considered address extensions that automatically select one of eight address spaces to which an ad- dress applies. these spaces are designated as either user or supervisor, and program or data spaces. because the cpu16 always operates in supervisor mode (fc2 always = 1), address spaces 0 to 3 are not used. address space 7 is designated cpu space. cpu space is used for control information not normally associated with read or write bus cycles. function codes are valid while as is asserted. table 14 displays cpu16 address space encodings. 3.5.3 address bus address bus signals addr[19:0] define the address of the most significant byte to be transferred during a bus cycle. the mcu places the address on the bus at the beginning of a bus cycle. the address is valid while as is asserted. because the cpu16 in the mc68hc16s2 does not drive addr[23:20], these lines follow the logic state of addr19. 3.5.4 address strobe as is a timing signal that indicates the validity of an address on the address bus and the validity of many control signals. it is asserted one-half clock after the beginning of a bus cycle. 3.5.5 data bus data bus signals data[15:0] make up a bidirectional, non-multiplexed parallel bus that transfers data to or from the mcu. a read or write operation can transfer eight or 16 bits of data in one bus cycle. dur- ing a read cycle, the data is latched by the mcu on the last falling edge of the clock for that bus cycle. for a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. the mcu places the data on the data bus one-half clock cycle after as is asserted in a write cycle. 3.5.6 data strobe data strobe (ds ) is a timing signal. for a read cycle, the mcu asserts ds to signal an external device to place data on the bus. ds is asserted at the same time as as during a read cycle. for a write cycle, ds signals an external device that data on the bus is valid. the mcu asserts ds one full clock cycle after the assertion of as during a write cycle. 3.5.7 bus cycle termination signals during bus cycles, external devices assert the data size acknowledge signals dsa ck1 and dsa ck0 . during a read cycle, the signals tell the mcu to terminate the bus cycle and to latch data. during a write cycle, the signals indicate that an external device has successfully stored data and that the cycle can end. these signals also indicate to the mcu the size of the port for the bus cycle just completed. alter- nately, chip-selects can be used to generate dsa ck1 and dsa ck0 internally. refer to 3.5.8 dynamic bus sizing for more information. table 14 cpu16 address space encoding fc2 fc1 fc0 address space 1 0 0 reserved 1 0 1 data space 1 1 0 program space 1 1 1 cpu space f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 26 mc68hc16s2ts/d the bus error (berr ) signal is also a bus cycle termination indicator and can be used in the absence of dsa ck1 and dsa ck0 to indicate a bus error condition. it can also be asserted in conjunction with these signals, provided it meets the appropriate timing requirements. the internal bus monitor can be used to generate the berr signal for internal-to-external transfers. when berr and hal t are assert- ed simultaneously, the cpu takes a bus error exception. the autovector signal (a vec ) can terminate irq pin interrupt acknowledge cycles. a vec indicates that the mcu will internally generate a vector number to locate an interrupt handler routine. if it is continu- ously asserted, autovectors will be generated for all external interrupt requests. a vec is ignored during all other bus cycles. 3.5.8 dynamic bus sizing the mcu dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8- and 16-bit ports. during an operand transfer cycle, the slave device sig- nals its port size and indicates completion of the bus cycle to the mcu through the use of the dsa ck1 and dsa ck0 inputs, as shown in table 15 . for example, if the mcu is executing an instruction that reads a long-word operand from a 16-bit port, the mcu latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits. the operation for an 8-bit port is similar, but requires four read cycles. the addressed device uses the dsa ck0 and dsa ck1 signals to indicate the port width. for instance, a 16-bit device always returns dsa ck0 = 1 and dsa ck1 = 0 for a 16-bit port, regardless of whether the bus cycle is a byte or word operation. dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. a 16-bit port must reside on data bus bits [15:0] and an 8-bit port must reside on data bus bits [15:8]. this minimizes the number of bus cycles needed to transfer data and ensures that the mcu transfers valid data. the mcu always attempts to transfer the maximum amount of data on all bus cycles. for a word oper- ation, it is assumed that the port is 16 bits wide when the bus cycle begins. operand bytes are desig- nated as shown in figure 10 . op0 is the most significant byte of a long-word operand, and op3 is the least significant byte. the two bytes of a word-length operand are op0 (most significant) and op1. the single byte of a byte-length operand is op0. table 15 effect of dsa ck signals dsa ck1 dsa ck0 result 1 1 insert wait states in current bus cycle 1 0 complete cycle ?data bus port size is 8 bits 0 1 complete cycle ?data bus port size is 16 bits 0 0 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 27 figure 10 operand byte order 3.5.9 operand alignment the data multiplexer establishes the necessary connections for different combinations of address and data sizes. the multiplexer takes the two bytes of the 16-bit bus and routes them to their required po- sitions. positioning of bytes is determined by the size and address outputs. siz1 and siz0 indicate the remaining number of bytes to be transferred during the current bus cycle. the number of bytes trans- ferred is equal to or less than the size indicated by siz1 and siz0, depending on port width. addr0 also affects the operation of the data multiplexer. during an operand transfer, addr[23:1] indicate the word base address of the portion of the operand to be accessed, and addr0 indicates the byte offset from the base. bear in mind the fact that addr[23:20] follow the state of addr19 in the mc68hc16s2. 3.5.10 misaligned operands cpu16 processor architecture uses a basic operand size of 16 bits. an operand is misaligned when it overlaps a word boundary. this is determined by the value of addr0. when addr0 = 0 (an even ad- dress), the address is on a word and byte boundary. when addr0 = 1 (an odd address), the address is on a byte boundary only. a byte operand is aligned at any address; a word or long-word operand is misaligned at an odd address. the largest amount of data that can be transferred by a single bus cycle is an aligned word. if the mcu transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the first bus cycle and the least significant operand word on a following bus cycle. the cpu16 can perform misaligned word transfers. this capability makes it software compatible with the m68hc11 cpu. the cpu16 treats misaligned long-word transfers as two misaligned word trans- fers. 3.5.11 operand transfer cases table 16 summarizes how operands are aligned for various types of transfers. opn entries are portions of a requested operand that are read or written during a bus cycle and are defined by siz1, siz0, and addr0 for that bus cycle. op0 operand byte order op1 op2 op3 24 31 23 16 15 8 7 0 byte order operand long word three byte word byte op2 op1 op0 op1 op0 op0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 28 mc68hc16s2ts/d 3.6 chip-selects typical microcontrollers require additional hardware to provide external chip-select and address de- code signals. the mc68hc16s2 includes 12 programmable chip-selects that can provide 2- to 16- clock-cycle access to external memory and peripherals. address block sizes of two kbytes to one mbyte can be selected. however, because addr[23:20] = addr19 in the cpu16, 512 kbyte blocks are the largest usable size. figure 11 is a functional diagram of a chip-select circuit. chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals. chip-select logic can also generate dsa ck and a vec signals internally. each signal can also be synchronized with the eclk signal available on addr23. notes: 1. operands in parentheses are ignored by the cpu16 during read cycles. 2. the cpu16 treats misaligned long-word transfers as two misaligned word transfers. 3. three byte transfer cases occur only as a result of an aligned long word to 8-bit port transfer. table 16 operand alignment current cycle transfer case siz1 siz0 addr0 dsa ck1 dsa ck0 data [15:8] data [7:0] next cycle 1 byte to 8-bit port (even) 0 1 0 1 0 op0 (op0) 1 2 byte to 8-bit port (odd) 0 1 1 1 0 op0 (op0) 3 byte to 16-bit port (even) 0 1 0 0 1 op0 (op0) 4 byte to 16-bit port (odd) 0 1 1 0 1 (op0) op0 5 word to 8-bit port (aligned) 1 0 0 1 0 op0 (op1) 2 6 word to 8-bit port (misaligned 1 0 1 1 0 op0 (op0) 1 7 word to 16-bit port (aligned) 1 0 0 0 1 op0 op1 8 word to 16-bit port (misaligned) 1 0 1 0 1 (op0) op0 3 9 long word to 8-bit port (aligned) 0 0 0 1 0 op0 (op1) 13 10 long word to 8-bit port (misaligned) 2 1 0 1 1 0 op0 (op0) 1 11 long word to 16-bit port (aligned) 0 0 0 0 1 op0 op1 7 12 long word to 16-bit port (misaligned) 2 1 0 1 0 1 (op0) op0 3 13 three byte to 8-bit port 3 1 1 1 1 0 op0 (op0) 5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 29 figure 11 chip-select circuit block diagram when a memory access occurs, chip-select logic compares address space type, address, type of ac- cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in chip-select registers. if all parameters match, the appropriate chip-select signal is asserted. select sig- nals are active low. if a chip-select function is given the same address as a microcontroller module or an internal memory array, an access to that address goes to the module or array, and the chip-select signal is not asserted. the external address and data buses do not reflect the internal access. all chip-select circuits except csboo t are disabled out of reset. chip-select option registers must not be written until base addresses have been written to the proper base address registers. alternate func- tions for chip-select pins are enabled if appropriate data bus pins are held low at the release of reset . table 17 lists allocation of chip-selects and discrete outputs on the pins of the mcu. table 17 chip-select and discrete output allocation pin chip-select discrete outputs csboo t csboo t ? br cs0 ? bg cs1 ? bga ck cs2 ? fc0 cs3 pc0 fc1 cs4 pc1 fc2 cs5 pc2 addr19 cs6 pc3 addr20 cs7 pc4 addr21 cs8 pc5 addr22 cs9 pc6 addr23 cs10 chip-sel block a vec generator dsa ck generator pin assignment register pin data register base address register timing and control address comparator option compare option register a vec dsa ck pin bus control internal signals address f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 30 mc68hc16s2ts/d 3.6.1 chip-select registers each chip-select pin can have one or more functions. chip-select pin assignment registers cspar[0:1] determine functions of the pins. pin assignment registers also determine port size for dynamic bus al- location. a pin data register (portc) latches data for chip-select pins that are used for discrete output. blocks of addresses are assigned to each chip-select function. block sizes of two kbytes to one mbyte can be selected by writing values to the appropriate base address registers csbarbt and csbar[0:10]. however, because the logic state of addr20 is always the same as the state of addr19 in the mc68hc16s2, the largest usable block size is 512 kbytes. multiple chip-selects assigned to the same block of addresses must have the same number of wait states. chip-select option registers csorbt and csor[0:10] determine timing of and conditions for assertion of chip-select signals. eight parameters, including operating mode, access size, synchronization, and wait state insertion can be specified. initialization software usually resides in a peripheral memory device controlled by the chip-select cir- cuits. csboo t and registers csorbt and csbarbt are provided to support bootstrap operation. 3.6.2 pin assignment registers the pin assignment registers contain twelve 2-bit fields that determine functions of the chip-select pins. each pin has two or three possible functions, as shown in table 18 . table 19 shows pin assignment field encoding. pins that have no discrete output function do not use the %00 encoding. table 18 chip-select pin functions assignment register 16-bit chip-select alternate function discrete output cspar0 csboo t csboo t ? cs0 br ? cs1 bg ? cs2 bga ck ? cs3 fc0 pc0 cs4 fc1 pc1 cs5 fc2 pc2 cspar1 cs6 addr19 pc3 cs7 addr20 pc4 cs8 addr21 pc5 cs9 addr22 pc6 cs10 addr23 eclk table 19 pin assignment encodings bit field description 00 discrete output 01 alternate function 10 chip-select (8-bit port) 11 chip-select (16-bit port) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 31 cspar0 contains seven 2-bit fields that determine the functions of corresponding chip-select pins. cspar0[15:14] are not used. these bits always read zero; writes have no effect. cspar0 bit 1 always reads one; writes to cspar0 bit 1 have no effect. table 20 shows cspar0 pin assignments. the reset state of data[7:3] determines whether pins controlled by cspar1 are initially configured as high-order address lines or chip-selects. table 21 shows the correspondence between data[7:3] and the reset configuration of cs[10:6] /addr[23:19]. notes: 1. refer to table 21 for cspar1 reset state information. cspar0 chip-select pin assignment register 0 $yffa44 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 cs5pa[1:0] cs4pa[1:0] cs3pa[1:0] cs2pa[1:0] cs1pa[1:0] cs0pa[1:0] csbtpa[1:0] reset: 0 0 data2 1 data2 1 data2 1 data1 1 data1 1 data1 1 1 data0 table 20 cspar0 pin assignments cspar0 field chip-select signal alternate signal discrete output cs5pa[1:0] cs5 fc2 pc2 cs4pa[1:0] cs4 fc1 pc1 cs3pa[1:0] cs3 fc0 pc0 cs2pa[1:0] cs2 bga ck cs1pa[1:0] cs1 bg cs0pa[1:0] cs0 br csbtpa[1:0] csboo t cspar1 chip-select pin assignment register 1 $yffa46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cs10pa[1:0] cs9pa[1:0] cs8pa[1:0] cs7pa[1:0] cs6pa[1:0] reset: 0 0 0 0 0 0 data7 1 1 data [7:6] 1 1 data [7:5] 1 1 data [7:4] 1 1 data [7:3] 1 1 table 21 reset pin function of cs[10:6] data bus pins at reset chip-select/address bus pin function data7 data6 data5 data4 data3 cs10 / addr23 cs9 / addr22 cs8 / addr21 cs7 / addr20 cs8 / addr19 11111 cs10 cs9 cs8 cs7 cs6 1111 0 cs10 cs9 cs8 cs7 addr19 111 0 x cs10 cs9 cs8 addr20 addr19 11 0 x x cs10 cs9 addr21 addr20 addr19 1 0 x x x cs10 addr22 addr21 addr20 addr19 0xxxx addr23 addr22 addr21 addr20 addr19 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 32 mc68hc16s2ts/d cspar1 contains five 2-bit fields that determine the functions of corresponding chip-select pins. cspar1[15:10] are not used. these bits always read zero; writes have no effect. table 22 shows cspar1 pin assignments. port size determines the way in which bus transfers to external addresses are allocated. port size of eight bits or sixteen bits can be selected when a pin is assigned as a chip-select. port size and transfer size affect how the chip-select signal is asserted. refer to 3.6.4 option registers for more information. out of reset, chip-select pin function is determined by the logic level on a corresponding data bus pin. these pins have weak internal pull-up drivers, but can be held low by external devices. either 16-bit chip-select function (%11) or alternate function (%01) can be selected during reset. all pins except the boot rom chip-select pin (csboo t ) are disabled out of reset. the csboo t signal is enabled out of reset. the state of the data0 line during reset determines what port width csboo t uses. if data0 is held high (either by the weak internal pull-up driver or by an ex- ternal pull-up device), 16-bit port size is selected. if data0 is held low, 8-bit port size is selected. a pin programmed as a discrete output drives an external signal to the value specified in the pin data register. no discrete output function is available on pins csboo t , br , bg , or bga ck . addr23 pro- vides eclk output rather than a discrete output signal. when a pin is programmed for discrete output or alternate function, internal chip-select logic still func- tions and can be used to generate dsa ck or a vec internally on an address and control signal match. 3.6.3 base address registers each chip-select has an associated base address register. a base address is the lowest address in the block of addresses enabled by a chip-select. block size is the extent of the address block above the base address. block size is determined by the value contained in the blksz field. multiple chip-selects may be assigned to the same block of addresses so long as each chip-select uses the same number of wait states. the blksz field determines which bits in the base address field are compared to corresponding bits on the address bus during an access. provided other constraints determined by option register fields are also satisfied, when a match occurs, the associated chip-select signal is asserted. after reset, the mcu fetches the address of the first instruction to be executed from the reset vector, located beginning at address $000000 in program space. to support bootstrap operation from reset, the base address field in csbarbt has a reset value of all zeros. a memory device containing the reset vector and an initialization routine can be automatically enabled by csboo t after a reset. the block size field in csbarbt has a reset value of 512 kbytes. table 22 cspar1 pin assignments cspar1 field chip-select signal alternate signal discrete output cs10pa[1:0] cs10 addr23 eclk cs9pa[1:0] cs9 addr22 pc6 cs8pa[1:0] cs8 addr21 pc5 cs7pa[1:0] cs7 addr20 pc4 cs6pa[1:0] cs6 addr19 pc3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 33 *addr[23:20] follow the state of addr19 in the mc68hc16s2. addr[23:20] must match addr19 in the base address register for the chip select to be active. addr[23:11] ?base address field this field sets the starting address of a particular address space. the address compare logic uses only the most significant bits to match an address within a block. the value of the base address must be an integer multiple of the block size. note because addr[23:20] = addr19 in the cpu16, maximum block size is 512 kbytes. for this same reason, addresses from $080000 to $f7ffff are inacces- sible. blocks can be based above this dead zone, but the effect of addr19 must be considered. blksz[2:0] ?block size field this field determines the size of the block that must be enabled by the chip-select. table 23 shows bit encoding for the base address registers block size field. addr[23:20] are at the same logic level as addr19 during normal operation. csbarbt chip-select base address register boot rom $yffa48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr 23 addr 22 addr 21 addr 20 addr 19 addr 18 addr 17 addr 16 addr 15 addr 14 addr 13 addr 12 addr 11 blksz[2:0] reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 csbar[0:10] chip-select base address registers $yffa4c?yffa74 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr 23* addr 22* addr 21* addr 20* addr 19 addr 18 addr 17 addr 16 addr 15 addr 14 addr 13 addr 12 addr 11 blksz[2:0] reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 23 block size field bit encoding blksz[2:0] block size address lines compared 000 2 kbyte addr[23:11] 001 8 kbyte addr[23:13] 010 16 kbyte addr[23:14] 011 64 kbyte addr[23:16] 100 128 kbyte addr[23:17] 101 256 kbyte addr[23:18] 110 512 kbyte addr[23:19] 111 512 kbyte addr[23:20] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 34 mc68hc16s2ts/d 3.6.4 option registers the option registers contain eight fields that determine timing of and conditions for assertion of chip- select signals. to assert a chip-select signal, and to provide dsa ck or autovector support, other con- straints set by fields in the option register and in the base address register must also be satisfied. csorbt, the option register for csboo t , contains special reset values that support bootstrap opera- tion from peripheral memory devices. the following bit descriptions apply to both csorbt and csor[0:10] option registers. mode ?asynchronous/synchronous mode 0 = asynchronous mode (chip-select assertion determined by bus control signals) 1 = synchronous mode (chip-select assertion synchronized with eclk signal) in asynchronous mode, the chip-select is asserted synchronized with as or ds . dsa ck[3:0] is not used in synchronous mode because a bus cycle is only performed as a synchronous operation. when a match condition occurs on a chip-select programmed for synchronous operation, the chip-select signals the ebi that an eclk cycle is pending. byte[1:0] ?upper/lower byte option this field is used only when the chip-select 16-bit port option is selected in the pin assignment register. table 24 lists upper/lower byte options. r/w [1:0] ?read/write this field causes a chip-select to be asserted only for reads, only for writes, or for both reads and writes. refer to table 25 for options available. csorbt chip-select option register boot rom $yffa4a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mode byte[1:0] r/ w [1:0] strb dsa ck[3:0] space[1:0] ipl[2:0] a vec reset: 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 csor[0:10] chip-select option registers $yffa4e?ffa76 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mode byte[1:0] r/ w [1:0] strb dsa ck[3:0] space[1:0] ipl[2:0] a vec reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 24 upper/lower byte options byte[1:0] description 00 disable 01 lower byte 10 upper byte 11 both bytes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 35 strb ?address strobe/data strobe 0 = address strobe 1 = data strobe this bit controls the timing for assertion of a chip-select in asynchronous mode. selecting address strobe causes chip-select to be asserted synchronized with address strobe. selecting data strobe caus- es chip-select to be asserted synchronized with data strobe. dsa ck[3:0] ?data and size acknowledge this field specifies the source of dsa ck in asynchronous mode. it also allows the user to adjust bus timing with internal dsa ck generation by controlling the number of wait states that are inserted to op- timize bus speed in a particular application. table 26 shows the dsa ck[3:0] encoding. the fast termi- nation encoding (%1110) is used for two-cycle access to external memory. space[1:0] ?address space use this option field to select an address space for the chip-select logic. the cpu16 normally operates in supervisor space, but interrupt acknowledge cycles must take place in cpu space. table 27 shows address space bit encodings. table 25 r/w encodings r/w [1:0] description 00 reserved 01 read only 10 write only 11 read/write table 26 dsa ck field encoding dsa ck[3:0] clock cycles required per access wait states per access 0000 3 0 wait states 0001 4 1 wait state 0010 5 2 wait states 0011 6 3 wait states 0100 7 4 wait states 0101 8 5 wait states 0110 9 6 wait states 0111 10 7 wait states 1000 11 8 wait states 1001 12 9 wait states 1010 13 10 wait states 1011 14 11 wait states 1100 15 12 wait states 1101 16 13 wait states 1110 2 fast termination 1111 external dsa ck f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 36 mc68hc16s2ts/d ipl[2:0] ?interrupt priority level if the space field is set for cpu space, chip-select logic can be used for interrupt acknowledge. during an interrupt acknowledge cycle, the priority level on address lines addr[3:1] is compared to the value in the ipl field. if the values are the same, a chip-select is asserted, provided that other option register conditions are met. table 28 shows ipl field encoding. this field only affects the response of chip-selects and does not affect interrupt recognition by the cpu. any level means that chip-select is asserted regardless of the level of the interrupt acknowledge cycle. a vec ?autovector enable 0 = external interrupt vector enabled 1 = autovector enabled this field selects one of two methods of acquiring an interrupt vector number during an external interrupt acknowledge cycle. if the chip-select is configured to trigger on an interrupt acknowledge cycle (space[1:0] = %00) and the a vec field is set to one, the chip-select circuit generates an internal a vec signal in response to an external interrupt cycle, and the sim supplies an automatic vector number. otherwise, the vector num- ber must be supplied by the requesting device. an internal autovector is generated only in response to interrupt requests from the sim irq pins. interrupt requests from other imb modules are ignored. the a vec bit must not be used in synchronous mode, as autovector response timing can vary because of eclk synchronization. 3.6.5 port c data register bit values in port c determine the state of chip-select pins used for discrete output. when a pin is as- signed as a discrete output, the value in this register appears at the output. this is a read/write register. bit 7 is not used. writing to this bit has no effect, and it always returns zero when read. table 27 address space bit encodings space[1:0] address space 00 cpu space 01 user space 10 supervisor space 11 supervisor/user space table 28 interrupt priority level field encoding ipl[2:0] interrupt priority level 000 any level 001 1 010 2 011 3 100 4 101 5 110 6 111 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 37 3.7 general-purpose input/output sim pins can be configured as two general-purpose i/o ports, e and f. the following paragraphs de- scribe registers that control the ports. a write to the port e data register is stored in the internal data latch and, if any port e pin is configured as an output, the value stored for that bit is driven on the pin. a read of the port e data register returns the value at the pin only if the pin is configured as a discrete input. otherwise, the value read is the value stored in the register. the port e data register is a single register that can be accessed in two locations. when accessed at $yffa11, the register is referred to as porte0; when accessed at $yffa13, the register is referred to as porte1. the register can be read or written at any time. it is unaffected by reset. the bits in this register control the direction of the pin drivers when the pins are configured as i/o. any bit in this register set to one configures the corresponding pin as an output. any bit in this register cleared to zero configures the corresponding pin as an input. this register can be read or written at any time. the bits in this register control the function of each port e pin. any bit set to one configures the corre- sponding pin as a bus control signal, with the function shown in table 29 . any bit cleared to zero defines the corresponding pin to be an i/o pin, controlled by porte and ddre. data bus bit 8 controls the state of this register following reset. if data8 is set to one during reset, the register is set to $ff, which defines all port e pins as bus control signals. if data8 is cleared to zero during reset, this register is set to $00, configuring all port e pins as i/o pins. portc port c data register $yffa41 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used 0 pc6 pc5 pc4 pc3 pc2 pc1 pc0 reset: 0 1 1 1 1 1 1 1 porte0, porte1 port e data register $yffa11, yffa13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 reset: u u u u u u u u ddre port e data direction register $yffa15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 reset: 0 0 0 0 0 0 0 0 pepar port e pin assignment $yffa17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pepa7 pepa6 pepa5 pepa4 pepa3 pepa2 pepa1 pepa0 reset: data8 data8 data8 data8 data8 data8 data8 data8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 38 mc68hc16s2ts/d a write to the port f data register is stored in the internal data latch, and if any port f pin is configured as an output, the value stored for that bit is driven onto the pin. a read of the port f data register returns the value at the pin only if the pin is configured as a discrete input. otherwise, the value read is the value stored in the register. the port f data register is a single register that can be accessed in two locations. when accessed at $yffa19, the register is referred to as portf0; when accessed at $yffa1b, the register is referred to as portf1. the register can be read or written at any time. it is unaffected by reset. the bits in this register control the direction of the pin drivers when the pins are configured as i/o. any bit in this register set to one configures the corresponding pin as an output. any bit in this register cleared to zero configures the corresponding pin as an input. this register can be read or written at any time. the bits in this register control the function of each port f pin. any bit cleared to zero defines the corre- sponding pin to be an i/o pin. any bit set to one defines the corresponding pin to be an interrupt request signal or modclk. the modclk signal has no function after reset. table 30 shows port f pin assign- ments. table 29 port e pin assignments pepar bit port e signal bus control signal pepa7 pe7 siz1 pepa6 pe6 siz0 pepa5 pe5 as pepa4 pe4 ds pepa3 pe3 pepa2 pe2 a vec pepa1 pe1 dsa ck1 pepa0 pe0 dsa ck0 portf0, portf1 port f data register $yffa19, yffa1b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset: u u u u u u u u ddrf port f data direction register $yffa1d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 reset: 0 0 0 0 0 0 0 0 pfpar port f pin assignment register $yffa1f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used pfpa7 pfpa6 pfpa5 pfpa4 pfpa3 pfpa2 pfpa1 pfpa0 reset: data9 data9 data9 data9 data9 data9 data9 data9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 39 data bus pin 9 controls the state of this register following reset. if data9 is set to one during reset, the register is set to $ff, which defines all port f pins as interrupt request inputs. if data9 is cleared to zero during reset, this register is set to $00, defining all port f pins as i/o pins. 3.8 resets reset procedures handle system initialization and recovery from catastrophic failure. the mcu per- forms resets with a combination of hardware and software. the sim determines whether a reset is valid, asserts control signals, performs basic system configuration based on hardware mode-select inputs, then passes control to the cpu. reset occurs when an active low logic level on the reset pin is clocked into the sim. resets are gated by the clkout signal. asynchronous resets are assumed to be catastrophic. an asynchronous reset can occur on any clock edge. synchronous resets are timed to occur at the end of bus cycles. if there is no clock when reset is asserted, reset does not occur until the clock starts. resets are clocked in order to allow completion of write cycles in progress at the time reset is asserted. reset is the highest-priority cpu16 exception. any processing in progress is aborted by the reset ex- ception, and cannot be restarted. only essential tasks are performed during reset exception processing. other initialization tasks must be accomplished by the exception handler routine. 3.8.1 sim reset mode selection the logic states of certain data bus pins during reset determine sim operating configuration. in addition, the state of the modclk pin determines system clock source and the state of the bkpt pin determines what happens during subsequent breakpoint assertions. table 31 is a summary of reset mode selection options. table 30 port f pin assignments pfpar field port f signal alternate signal pfpa7 pf7 irq7 pfpa6 pf6 irq6 pfpa5 pf5 irq5 pfpa4 pf4 irq4 pfpa3 pf3 irq3 pfpa2 pf2 irq2 pfpa1 pf1 irq1 pfpa0 pf0 modclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 40 mc68hc16s2ts/d data lines have weak internal pull-up drivers. external bus loading can overcome the weak internal pull- up drivers on data bus lines, and hold pins low during reset. use an active device to hold data bus lines low. data bus configuration logic must release the bus before the first bus cycle after reset to prevent conflict with external memory devices. the first bus cycle occurs ten clkout cycles after reset is released. if external mode selection logic causes a conflict of this type, an isolation resistor on the driven lines may be required. 3.8.2 functions of pins for other modules during reset generally, pins associated with modules other than the sim default to port functions, and input/output ports are set to input state. this is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers. refer to individual module sec- tions in this manual for more information. table 32 is a summary of module pin function out of reset. 3.8.3 reset timing the reset input must be asserted for a specified minimum period in order for reset to occur. external reset assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor timeout period) in order to protect write cycles from being aborted by reset. while reset is asserted, sim pins are either in a disabled high-impedance state or are driven to their inactive states. table 31 reset mode selection mode select pin default function (pin left high) alternate function (pin pulled low) data0 csboo t 16-bit csboo t 8-bit data1 cs0 cs1 cs2 br bg bga ck data2 cs3 cs4 cs5 fc0 fc1 fc2 data3 data4 data5 data6 data7 cs6 cs[7:6] cs[8:6] cs[9:6] cs[10:6] addr19 addr[20:19] addr[21:19] addr[22:19] addr[23:19] data8 dsa ck[1:0] a vec , ds , as siz[1:0] porte data9 irq[7:1] modclk portf data11 test mode disabled test mode enabled modclk vco = system clock extal = system clock bkpt background mode disabled background mode enabled table 32 module pin functions module pin mnemonic function cpu16 dsi/ipipe1 dsi/ipipe1 dso/ipipe0 dso/ipipe0 bkpt /dsclk bkpt /dsclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 41 when an external device asserts reset for the proper period, reset control logic clocks the signal into an internal latch. the control logic drives the reset pin low for an additional 512 clkout cycles after it detects that the reset signal is no longer being externally driven, to guarantee this length of reset to the entire system. if an internal source asserts the reset signal, the reset control logic asserts reset for a minimum of 512 cycles. if the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert reset until the internal reset signal is negated. after 512 cycles have elapsed, the reset pin goes to an inactive, high-impedance state for ten cycles. at the end of this 10-cycle period, the reset pin is tested. when the input is at logic level one, reset exception processing begins. if, however, the reset pin is at logic level zero, the reset control logic drives the pin low for another 512 cycles. at the end of this period, the pin again goes to high-impedance state for ten cycles, then it is tested again. the process repeats until reset is released. 3.8.4 power-on reset when the sim clock synthesizer is used to generate the system clock, power-on reset involves special circumstances related to application of system and clock synthesizer power. regardless of clock source, voltage must be applied to clock synthesizer power input pin v ddsyn in order for the mcu to operate. the following discussion assumes that v ddsyn is applied before and during reset. this mini- mizes crystal start-up time. when v ddsyn is applied at power-on, start-up time is affected by specific crystal parameters and by oscillator circuit design. v dd ramp-up time also affects pin state during reset. during power-on reset, an internal circuit in the sim drives the imb and external reset lines. the circuit releases the internal reset line as v dd ramps up to the minimum specified value, and sim pins are ini- tialized. as v dd reaches a specified minimum value, the clock synthesizer vco begins operation and clock frequency ramps up to specified limp mode frequency. the external reset line remains asserted until the clock synthesizer pll locks and 512 clkout cycles elapse. the sim clock synthesizer provides clock signals to the other mcu modules. after the clock is running and the internal reset signal is asserted for four clock cycles, these modules reset. v dd ramp time and vco frequency ramp time determine how long these four cycles take. worst case is approximately 15 milliseconds. during this period, module port pins may be in an indeterminate state. while input-only pins can be put in a known state by means of external pull-up resistors, external logic on input/output or output-only pins must condition the lines during this time. active drivers require high-impedance buff- ers or isolation resistors to prevent conflict. 3.8.5 use of three-state control pin asserting the three-state control (tsc) input causes the mcu to put all output drivers in an inactive, high-impedance state. the signal must remain asserted for ten clock cycles in order for drivers to change state. there are certain constraints on use of tsc during power-on reset: ?when the internal clock synthesizer is used (modclk held high during reset), synthesizer ramp- up time affects how long the ten cycles take. worst case is approximately 20 ms from tsc asser- tion. ?when an external clock signal is applied (modclk held low during reset), pins go to high-imped- ance state as soon after tsc assertion as ten clock pulses have been applied to the extal pin. ?when tsc assertion takes effect, internal signals are forced to values that can cause inadvertent mode selection. once the output drivers change state, the mcu must be powered down and re- started before normal operation can resume. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 42 mc68hc16s2ts/d 3.9 interrupts interrupt recognition and servicing involve complex interaction between the cpu16, the sim, and a de- vice or module requesting interrupt service. the cpu16 provides seven levels of interrupt priority (1?), seven automatic interrupt vectors, and 200 assignable interrupt vectors. all interrupts with priorities less than seven can be masked by the interrupt priority (ip) field in the condition code register. the cpu16 handles interrupts as a type of asynchronous expression. there are seven interrupt request signals (irq[7:1] ). these signals are used internally on the imb, and there are corresponding pins for external interrupt service requests. the cpu treats all interrupt re- quests as though they come from internal modules ?external interrupt requests are treated as interrupt service requests from the sim. each of the interrupt request signals corresponds to an interrupt priority level. irq1 has the lowest priority and irq7 the highest. interrupt recognition is determined by interrupt priority level and interrupt priority mask value. the inter- rupt priority mask consists of three bits (ip[2:0]) in the cpu16 condition code register. binary values %000 to %111 provide eight priority masks. masks prevent an interrupt request of a priority less than or equal to the mask value from being recognized and processed. irq7 , however, is always recognized, even if the mask value is %111. irq[7:1] are active-low level-sensitive inputs. the low on the pin must remain asserted until an interrupt acknowledge cycle corresponding to that level is detected. irq7 is transition-sensitive as well as level-sensitive: a level 7 interrupt is not detected unless a falling edge transition is detected on the irq7 line. this prevents redundant servicing and stack overflow. a non-maskable interrupt is generated each time irq7 is asserted as well as each time the priority mask changes from %111 to a lower number while irq7 is asserted. interrupt requests are sampled on consecutive falling edges of the system clock. interrupt request input circuitry has hysteresis: to be valid, a request signal must be asserted for at least two consecutive clock periods. valid requests do not cause immediate exception processing, but are left pending. pending re- quests are processed at instruction boundaries or when exception processing of higher-priority excep- tions is complete. the cpu16 does not latch the priority of a pending interrupt request. if an interrupt source of higher priority makes a service request while a lower priority request is pending, the higher priority request is serviced. if an interrupt request with a priority equal to or lower than the current ip mask value is made, the cpu16 does not recognize the occurrence of the request. if simultaneous interrupt requests of dif- ferent priorities are made, and both have a priority greater than the mask value, the cpu16 recognizes the higher-level request. 3.9.1 interrupt acknowledge and arbitration when the cpu16 detects one or more interrupt requests of a priority higher than the interrupt priority mask value, it places the interrupt request level on the address bus and initiates a cpu space read cy- cle. the request level serves two purposes: it is decoded by modules or external devices that have re- quested interrupt service, to determine whether the current interrupt acknowledge cycle pertains to them, and it is latched into the ip mask field in the cpu16 condition code register, to preclude further interrupts of lower priority during interrupt service. modules or external devices that have requested interrupt service must decode the interrupt priority mask value placed on the address bus during the interrupt acknowledge cycle and respond if the priority of the service request corresponds to the mask value. however, before modules or external devices respond, interrupt arbitration takes place. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 43 arbitration is performed by means of serial contention between values stored in individual module inter- rupt arbitration (iarb) fields. each module that can request interrupt service, including the sim, has an iarb field in its configuration register. iarb fields can be assigned values from %0000 to %1111. in order to implement an arbitration scheme, each module that can request interrupt service must be assigned a unique, non-zero iarb field value during system initialization. arbitration priorities range from %0001 (lowest) to %1111 (highest) ?if the cpu recognizes an interrupt service request from a source that has an iarb field value of %0000, a spurious interrupt exception is processed. warning do not assign the same arbitration priority to more than one module. when two or more iarb fields have the same non-zero value, the cpu16 interprets multiple vector numbers at the same time, with unpredictable consequences. because the ebi manages external interrupt requests, the sim iarb value is used for arbitration be- tween internal and external interrupt requests. the reset value of iarb for the sim is %1111, and the reset iarb value for all other modules is %0000. although arbitration is intended to deal with simultaneous requests of the same priority, it always takes place, even when a single source is requesting service. this is important for two reasons: the ebi does not transfer the interrupt acknowledge read cycle to the external bus unless the sim wins contention, and failure to contend causes the interrupt acknowledge bus cycle to be terminated early, by a bus error. when arbitration is complete, the module with the highest arbitration priority must terminate the bus cycle. internal modules place an interrupt vector number on the data bus and generate appropriate in- ternal cycle termination signals. in the case of an external interrupt request, after the interrupt acknowl- edge cycle is transferred to the external bus, the appropriate external device must decode the mask value and respond with a vector number, then generate data and size acknowledge (dsa ck ) termina- tion signals, or it must assert the autovector (a vec ) request signal. if the device does not respond in time, the ebi bus monitor asserts the bus error signal (berr ), and a spurious interrupt exception is taken. chip-select logic can also be used to generate internal a vec or dsa ck signals in response to interrupt requests from external devices. chip-select address match logic functions only after the ebi transfers an interrupt acknowledge cycle to the external bus following iarb contention. if a module makes an interrupt request of a certain priority, and the appropriate chip-select registers are programmed to gen- erate a vec or dsa ck signals in response to an interrupt acknowledge cycle for that priority level, chip- select logic does not respond to the interrupt acknowledge cycle, and the internal module supplies a vector number and generates internal cycle termination signals. for periodic timer interrupts, the pirql field in the periodic interrupt control register (picr) determines pit priority level. a pirql value of %000 means that pit interrupts are inactive. by hardware conven- tion, when the cpu16 receives simultaneous interrupt requests of the same level from more than one sim source (including external devices), the periodic interrupt timer is given the highest priority, followed by the irq pins. refer to 3.4.6 periodic interrupt timer for more information. 3.9.2 interrupt processing summary a summary of the interrupt processing sequence follows. when the sequence begins, a valid interrupt service request has been detected and is pending. a. the cpu finishes higher priority exception processing or reaches an instruction boundary. b. the processor state is stacked, then the ccr pk extension field is cleared. c. the interrupt acknowledge cycle begins: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 44 mc68hc16s2ts/d 1. fc[2:0] are driven to %111 (cpu space) encoding. 2. the address bus is driven as follows: addr[23:20] = %1111; addr[19:16] = %1111, which indicates that the cycle is an interrupt acknowledge cpu space cycle; addr[15:4] = %111111111111; addr[3:1] = the priority of the interrupt request being acknowledged; and addr0 = %1. 3. the request level is latched from the address bus into the ip mask field in the condition code register. d. modules or external peripherals that have requested interrupt service decode the priority value on addr[3:1]. if request priority is the same as acknowledged priority, arbitration by iarb contention takes place. e. after arbitration, the interrupt acknowledge cycle is completed in one of the following ways: 1. when there is no contention (iarb = %0000), the spurious interrupt monitor asserts berr , and the cpu16 generates the spurious interrupt vector number. 2. the dominant interrupt source supplies a vector number and dsa ck signals appropriate to the access. the cpu16 acquires the vector number. 3. the internal a vec signal is asserted by the dominant interrupt source and the cpu16 gen- erates an autovector number corresponding to interrupt priority. 4. the bus monitor asserts berr and the cpu16 generates the spurious interrupt vector number. f. the vector number is converted to a vector address. g. the content of the vector address is loaded into the pc, and the processor transfers control to the exception handler routine. 3.10 factory test block the test submodule supports scan-based testing of the various mcu modules. it is integrated into the sim to support production testing. test submodule registers are intended for motorola use. register names and addresses are provided to indicate that these addresses are occupied. simtr system integration module test register $yffa02 simtre ? system integration module test register (e clock) $yffa08 tstmsra ? master shift register a $yffa30 tstmsrb ? master shift register b $yffa32 tstsc ? test module shift count $yffa34 tstrc ? test module repetition count $yffa36 creg ? test module control register $yffa38 dreg ? test module distributed register $yffa3a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 45 4 central processing unit the cpu16 is a true 16-bit, high-speed device. it was designed to give m68hc11 users a path to higher performance while maintaining maximum compatibility with existing systems. 4.1 overview the cpu16 instruction set is optimized for high performance. there are two 16-bit general-purpose ac- cumulators and three 16-bit index registers. the cpu16 supports 8-bit (byte), 16-bit (word), and 32-bit (long-word) load and store operations, as well as 16- and 32-bit signed fractional operations. code de- velopment is simplified by the background debugging mode. cpu16 memory space includes a one mbyte data space and a one mbyte program space. twenty-bit addressing and transparent bank switching are used to implement extended memory. in addition, most instructions automatically handle bank boundaries. the cpu16 includes instructions and hardware to implement control-oriented digital signal processing functions with a minimum of interfacing. a multiply and accumulate unit provides the capability to mul- tiply signed 16-bit fractional numbers and store the resulting 32-bit fixed point product in a 36-bit accu- mulator. modulo addressing supports finite impulse response filters. use of high-level languages is increasing as controller applications become more complex and control programs become larger. these languages make rapid development of portable software possible. the cpu16 instruction set supports high-level languages. 4.2 m68hc11 compatibility the cpu16 architecture is a superset of the m68hc11 cpu architecture. all m68hc11 cpu resources are available in the cpu16. m68hc11 cpu instructions are either directly implemented in the cpu16, or have been replaced by instructions with an equivalent form. the instruction sets are source code compatible, but some instructions are executed differently in the cpu16. these instructions are mainly related to interrupt and exception processing ?m68hc11 cpu code that processes interrupts, handles stack frames, or manipulates the condition code register must be rewritten. cpu16 execution times and number of cycles for all instructions are different from those of the m68hc11 cpu. as a result, cycle-related delays and timed control routines may be affected. the cpu16 also has several new or enhanced addressing modes. m68hc11 cpu direct mode ad- dressing has been replaced by a special form of indexed addressing that uses the new iz register and a reset vector to provide greater flexibility. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 46 mc68hc16s2ts/d 4.3 programming model figure 12 cpu16 programming model 20 16 15 8 7 0 bit position a b accumulators a and b d accumulator d (a : b) e accumulator e xk ix index register x yk iy index register y zk iz index register z sk sp stack pointer pk pc program counter ccr pk condition code register pc extension register ek xk yk zk address extension register sk stack extension register hr mac multiplier register ir mac multiplicand register 35 16 am (msb) mac accumulatormsb [35:16] am (lsb) mac accumulator lsb [15:0] xmsk ymsk mac xy mask register accumulator a ?8-bit general-purpose register accumulator b ?8-bit general-purpose register accumulator d ?16-bit general-purpose register formed by concatenating accumulators a and b accumulator e ?16-bit general-purpose register index register x ?16-bit indexing register, addressing extended by xk field in k register index register y ?16-bit indexing register, addressing extended by yk field in k register index register z ?16-bit indexing register, addressing extended by zk field in k register stack pointer ?16-bit dedicated register, addressing extended by the sk register program counter ?16-bit dedicated register, addressing extended by pk field in ccr condition code register ?16-bit register containing condition flags, interrupt priority mask, and the program counter address extension field k register ?16-bit register made up of four 4-bit address extension fields sk register ?4-bit register containing the stack pointer address extension field h register ?16-bit multiply and accumulate input (multiplier) register i register ?16-bit multiply and accumulate input (multiplicand) register mac accumulator ?36-bit multiply and accumulate result register xmsk, ymsk ?determine which bits change when an offset is added f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 47 4.3.1 condition code register s ?stop enable 0 = stop clock when lpstop instruction is executed 1 = perform nop when lpstop instruction is executed mv ?accumulator m overflow flag mv is set when an overflow into am35 has occurred. h ?half carry flag h is set when a carry from a3 or b3 occurs during bcd addition. ev ?extension bit overflow flag ev is set when an overflow into am31 has occurred. n ?negative flag n is set when the msb of a result register is set. z ?zero flag z is set when all bits of a result register are zero. v ?overflow flag v is set when a two? complement overflow occurs as the result of an operation. c ?carry flag c is set when a carry or borrow occurs during an arithmetic operation. this flag is also used during shift and rotate to facilitate multiple word operations. ip[2:0] ?interrupt priority field the priority value in this field (0 to 7) is used to mask interrupts. sm ?saturate mode bit when sm is set, if either ev or mv is set, data read from am using tmer or tmet is given maximum positive or negative value, depending on the state of the am sign bit before overflow. pk[3:0] ?program counter address extension field this field is concatenated with the program counter to form a 20-bit address. 4.4 data types the cpu16 supports the following data types: ?bit data ?8-bit (byte) and 16-bit (word) integers ?32-bit long integers ?16-bit and 32-bit signed fractions (mac operations only) ?20-bit effective address consisting of 16-bit page address plus 4-bit extension a byte is eight bits wide and can be accessed at any byte location. a word is composed of two consec- utive bytes, and is addressed at the lower byte. instruction fetches are always accessed on word bound- aries. word operands are normally accessed on word boundaries as well, but can be accessed on odd byte boundaries, with a substantial performance penalty. to be compatible with the m68hc11, misaligned word transfers and misaligned stack accesses are al- lowed. transferring a misaligned word requires two successive byte operations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s mv h ev n z v c ip[2:0] sm pk[3:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 48 mc68hc16s2ts/d 4.5 addressing modes the cpu16 provides ten types of addressing. each type encompasses one or more addressing modes. six cpu16 addressing types are identical to m68hc11 addressing types. all modes generate addr[15:0]. this address is combined with addr[19:16] from an extension field to form a 20-bit effective address. extension fields are part of a bank switching scheme that provides the cpu16 with a one mbyte address space. bank switching is transparent to most instructions. ad- dr[19:16] of the effective address change when an access crosses a bank boundary. however, it is important to note that the value of the associated extension field is dependent on the type of instruction, and usually does not change as a result of effective address calculation. in the immediate modes, the instruction argument is contained in bytes or words immediately following the instruction. the effective address is the address of the byte following the instruction. the ais, aix/ y/z, addd and adde instructions have an extended 8-bit mode where the immediate value is an 8-bit signed number that is sign-extended to 16 bits, and then added to the appropriate register. use of the extended 8-bit mode decreases execution time. extended mode instructions contain addr[15:0] in the word following the opcode. the effective ad- dress is formed by concatenating ek and the 16-bit extension. in the indexed modes, registers ix, iy, and iz, together with their associated extension fields, are used to calculate the effective address. signed 16-bit mode and signed 20-bit mode are extensions to the m68hc11 indexed addressing mode. for 8-bit indexed mode, an 8-bit unsigned offset contained in the instruction is added to the value con- tained in the index register and its associated extension field. for 16-bit mode, a 16-bit signed offset contained in the instruction is added to the value contained in the index register and its associated extension field. for 20-bit mode, a 20-bit signed offset is added to the value contained in the index register. this mode is used for jmp and jsr instructions. inherent mode instructions use information available to the processor to determine the effective ad- dress. operands (if any) are system resources and are thus not fetched from memory. accumulator offset mode adds the contents of 16-bit accumulator e to one of the index registers and its associated extension field to form the effective address. this mode allows use of index registers and an accumulator within loops without corrupting accumulator d. relative modes are used for branch and long branch instructions. a byte or word signed two's comple- ment offset is added to the program counter if the branch condition is satisfied. the new pc value, con- catenated with the pk field, is the effective address. post-modified index mode is used with the movb and movw instructions. a signed 8-bit offset is add- ed to index register x after the effective address formed by xk and ix is used. in m68hc11 systems, direct mode can be used to perform rapid accesses to ram or i/o mapped into page 0 ($0000 to $00ff), but the cpu16 uses the first 512 bytes of page 0 for exception vectors. to compensate for the loss of direct mode, the zk field and index register z have been assigned reset ini- tialization vectors. by resetting the zk field to a chosen page, and using 8-bit unsigned index mode with iz, a programmer can access useful data structures anywhere in the address map. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 49 4.6 instruction set the cpu16 instruction set is based on that of the m68hc11, but the opcode map has been rearranged to maximize performance with a 16-bit data bus. all m68hc11 instructions are supported by the cpu16, although they may be executed differently. most m68hc11 code runs on the cpu16 following reassem- bly. however, take into account changed instruction times, the interrupt mask, and the new interrupt stack frame. the cpu16 has a full range of 16-bit arithmetic and logic instructions, including signed and unsigned multiplication and division. new instructions have been added to support extended addressing and dig- ital signal processing. table 33 is a quick reference to the entire cpu16 instruction set. because it is only affected by a few instructions, the lsb of the condition code register is not shown in the table. instructions that affect the interrupt mask and pk field are noted. table 34 provides a key to the table nomenclature. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 50 mc68hc16s2ts/d table 33 instruction set summary mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c aba add b to a (a ) + (b) t a inh 370b 2 d dddd abx add b to ix (xk : ix) + (000 : b) t xk : ix inh 374f 2 aby add b to iy (yk : iy) + (000 : b) t yk : iy inh 375f 2 abz add b to iz (zk : iz) + (000 : b) t zk : iz inh 376f 2 ace add e to am (am[31:16]) + (e) t am inh 3722 2 d d aced add e : d to am (am) + (e : d) t am inh 3723 4 d d adca add with carry to a (a) + (m) + c t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 43 53 63 73 1743 1753 1763 1773 2743 2753 2763 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d dddd adcb add with carry to b (b) + (m) + c t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c3 d3 e3 f3 17c3 17d3 17e3 17f3 27c3 27d3 27e3 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d dddd adcd add with carry to d (d) + (m : m + 1) + c t d ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext e, x e, y e, z 83 93 a3 37b3 37c3 37d3 37e3 37f3 2783 2793 27a3 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 6 6 6 dddd adce add with carry to e (e) + (m : m + 1) + c t e imm16 ind16, x ind16, y ind16, z ext 3733 3743 3753 3763 3773 jj kk gggg gggg gggg hh ll 4 6 6 6 6 dddd adda add to a (a) + (m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 41 51 61 71 1741 1751 1761 1771 2741 2751 2761 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d dddd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 51 addb add to b (b) + (m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c1 d1 e1 f1 17c1 17d1 17e1 17f1 27c1 27d1 27e1 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d dddd addd add to d (d) + (m : m + 1) t d ind8, x ind8, y ind8, z imm8 imm16 ind16, x ind16, y ind16, z ext e, x e, y e, z 81 91 a1 fc 37b1 37c1 37d1 37e1 37f1 2781 2791 27a1 ff ff ff ii jj kk gggg gggg gggg hh ll 6 6 6 2 4 6 6 6 6 6 6 6 dddd adde add to e (e) + (m : m + 1) t e imm8 imm16 ind16, x ind16, y ind16, z ext 7c 3731 3741 3751 3761 3771 ii jj kk gggg gggg gggg hh ll 2 4 6 6 6 6 dddd ade add d to e (e) + (d) t e inh 2778 2 dddd adx add d to ix inh 37cd 2 ady add d to iy inh 37dd 2 adz add d to iz inh 37ed 2 aex add e to ix inh 374d 2 aey add e to iy inh 375d 2 aez add e to iz inh 376d 2 ais add immediate data to stack pointer (sk : sp) + (20 ?imm) t sk : sp imm8 imm16 3f 373f ii jj kk 2 4 aix add immediate value to ix (xk : ix) + (20 ?imm) t xk : ix imm8 imm16 3c 373c ii jj kk 2 4 d aiy add immediate value to iy (yk : iy) + (20 ?imm) t yk : iy imm8 imm16 3d 373d ii jj kk 2 4 d aiz add immediate value to iz (zk : iz) + (20 ?imm) t zk : iz imm8 imm16 3e 373e ii jj kk 2 4 d anda and a (a) (m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 46 56 66 76 1746 1756 1766 1776 2746 2756 2766 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dd 0 table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c xk : ix () 20 d () xk : ix t + yk : iy () 20 d () yk : iy t + zk : iz () 20 d () zk : iz t + xk : ix () 20 d () xk : ix t + yk : iy () 20 d () yk : iy t + zk : iz () 20 d () zk : iz t + f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 52 mc68hc16s2ts/d andb and b (b) (m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c6 d6 e6 f6 17c6 17d6 17e6 17f6 27c6 27d6 27e6 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dd 0 andd and d (d) (m : m + 1) t d ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext e, x e, y e, z 86 96 a6 37b6 37c6 37d6 37e6 37f6 2786 2796 27a6 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 6 6 6 dd 0 ande and e (e) (m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3736 3746 3756 3766 3776 jj kk gggg gggg gggg hh ll 4 6 6 6 6 dd 0 andp 1 and ccr (ccr) imm16 t ccr imm16 373a jj kk 4 d d d d dddd asl arithmetic shift left ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 04 14 24 1704 1714 1724 1734 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 dddd asla arithmetic shift left a inh 3704 2 dddd aslb arithmetic shift left b inh 3714 2 dddd asld arithmetic shift left d inh 27f4 2 dddd asle arithmetic shift left e inh 2774 2 dddd aslm arithmetic shift left am inh 27b6 4 d dd d aslw arithmetic shift left word ind16, x ind16, y ind16, z ext 2704 2714 2724 2734 gggg gggg gggg hh ll 8 8 8 8 dddd asr arithmetic shift right ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 0d 1d 2d 170d 171d 172d 173d ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 dddd asra arithmetic shift right a inh 370d 2 dddd table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 53 asrb arithmetic shift right b inh 371d 2 dddd asrd arithmetic shift right d inh 27fd 2 dddd asre arithmetic shift right e inh 277d 2 dddd asrm arithmetic shift right am inh 27ba 4 dd d asrw arithmetic shift right word ind16, x ind16, y ind16, z ext 270d 271d 272d 273d gggg gggg gggg hh ll 8 8 8 8 dddd bcc 2 branch if carry clear if c = 0, branch rel8 b4 rr 6, 2 bclr clear bit(s) (m) (mask ) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 1708 1718 1728 08 18 28 38 mm ff mm ff mm ff mm gggg mm gggg mm gggg mm hh ll 8 8 8 8 8 8 8 dd 0 bclrw clear bit(s) in a word (m : m + 1) (mask ) t m : m + 1 ind16, x ind16, y ind16, z ext 2708 2718 2728 2738 gggg mmmm gggg mmmm gggg mmmm hh ll mmmm 10 10 10 10 dd 0 bcs 2 branch if carry set if c = 1, branch rel8 b5 rr 6, 2 beq 2 branch if equal if z = 1, branch rel8 b7 rr 6, 2 bge 2 branch if greater than or equal to zero if n ? v = 0, branch rel8 bc rr 6, 2 bgnd enter background debug mode if bdm enabled, begin debug; else, illegal instruction trap inh 37a6 bgt 2 branch if greater than zero if z ; (n ? v) = 0, branch rel8 be rr 6, 2 bhi 2 branch if higher if c ; z = 0, branch rel8 b2 rr 6, 2 bita bit test a (a) (m) ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 49 59 69 79 1749 1759 1769 1779 2749 2759 2769 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dd 0 bitb bit test b (b) (m) ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c9 d9 e9 f9 17c9 17d9 17e9 17f9 27c9 27d9 27e9 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dd 0 ble 2 branch if less than or equal to zero if z ; (n ? v) = 1, branch rel8 bf rr 6, 2 table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 54 mc68hc16s2ts/d bls 2 branch if lower or same if c ; z = 1, branch rel8 b3 rr 6, 2 blt 2 branch if less than zero if n ? v = 1, branch rel8 bd rr 6, 2 bmi 2 branch if minus if n = 1, branch rel8 bb rr 6, 2 bne 2 branch if not equal if z = 0, branch rel8 b6 rr 6, 2 bpl 2 branch if plus if n = 0, branch rel8 ba rr 6, 2 bra branch always if 1 = 1, branch rel8 b0 rr 6 brclr 2 branch if bit(s) clear if (m) (mask) = 0, branch ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext cb db eb 0a 1a 2a 3a mm ff rr mm ff rr mm ff rr mm gggg rrrr mm gggg rrrr mm gggg rrrr mm hh ll rrrr 10, 12 10, 12 10, 12 10, 14 10, 14 10, 14 10, 14 brn branch never if 1 = 0, branch rel8 b1 rr 2 brset 2 branch if bit(s) set if (m ) ?(mask) = 0, branch ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8b 9b ab 0b 1b 2b 3b mm ff rr mm ff rr mm ff rr mm gggg rrrr mm gggg rrrr mm gggg rrrr mm hh ll rrrr 10, 12 10, 12 10, 12 10, 14 10, 14 10, 14 10, 14 bset set bit(s) (m) ; (mask) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 1709 1719 1729 09 19 29 39 mm ff mm ff mm ff mm gggg mm gggg mm gggg mm hh ll 8 8 8 8 8 8 8 dd 0 d bsetw set bit(s) in word (m : m + 1) ; (mask) t m : m + 1 ind16, x ind16, y ind16, z ext 2709 2719 2729 2739 gggg mmmm gggg mmmm gggg mmmm hh ll mmmm 10 10 10 10 dd 0 d bsr branch to subroutine (pk : pc) - 2 t pk : pc push (pc) (sk : sp) - 2 t sk : sp push (ccr) (sk : sp) - 2 t sk : sp (pk : pc) + offset t pk : pc rel8 36 rr 10 bvc 2 branch if overflow clear if v = 0, branch rel8 b8 rr 6, 2 bvs 2 branch if overflow set if v = 1, branch rel8 b9 rr 6, 2 cba compare a to b (a) - (b) inh 371b 2 dddd clr clear a byte in memory $00 t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 05 15 25 1705 1715 1725 1735 ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 0100 clra clear a $00 t a inh 3705 2 0100 clrb clear b $00 t b inh 3715 2 0100 clrd clear d $0000 t d inh 27f5 2 0100 clre clear e $0000 t e inh 2775 2 0100 table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 55 clrm clear am $000000000 t am[35:0] inh 27b7 2 0 0 clrw clear a word in memory $0000 t m : m + 1 ind16, x ind16, y ind16, z ext 2705 2715 2725 2735 gggg gggg gggg hh ll 6 6 6 6 0100 cmpa compare a to memory (a) - (m) ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 48 58 68 78 1748 1758 1768 1778 2748 2758 2768 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dddd cmpb compare b to memory (b) - (m) ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c8 d8 e8 f8 17c8 17d8 17e8 17f8 27c8 27d8 27e8 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dddd com one? complement $ff - (m) t m, or m t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 00 10 20 1700 1710 1720 1730 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 dd 01 coma one? complement a $ff - (a) t a, or m t a inh 3700 2 dd 01 comb one? complement b $ff - (b) t b, or b t b inh 3710 2 dd 01 comd one? complement d $ffff - (d) t d, or d t d inh 27f0 2 dd 01 come one? complement e $ffff - (e) t e, or e t e inh 2770 2 dd 01 comw one? complement word $ffff - m : m + 1 t m : m + 1, or (m : m + 1 ) t m : m + 1 ind16, x ind16, y ind16, z ext 2700 2710 2720 2730 gggg gggg gggg hh ll 8 8 8 8 dd 01 cpd compare d to memory (d) - (m : m + 1) ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext e, x e, y e, z 88 98 a8 37b8 37c8 37d8 37e8 37f8 2788 2798 27a8 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 6 6 6 dddd cpe compare e to memory (e) - (m : m + 1) imm16 ind16, x ind16, y ind16, z ext 3738 3748 3758 3768 3778 jjkk gggg gggg gggg hhll 4 6 6 6 6 dddd cps compare stack pointer to memory (sp) - (m : m + 1) ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext 4f 5f 6f 377f 174f 175f 176f 177f ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 dddd table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 56 mc68hc16s2ts/d cpx compare ix to memory (ix) - (m : m + 1) ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext 4c 5c 6c 377c 174c 175c 176c 177c ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 dddd cpy compare iy to memory (iy) - (m : m + 1) ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext 4d 5d 6d 377d 174d 175d 176d 177d ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 dddd cpz compare iz to memory (iz) - (m : m + 1) ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext 4e 5e 6e 377e 174e 175e 176e 177e ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 dddd daa decimal adjust a (a) 10 inh 3721 2 dd u d dec decrement memory (m) - $01 t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 01 11 21 1701 1711 1721 1731 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 ddd deca decrement a (a) - $01 t a inh 3701 2 ddd decb decrement b (b) - $01 t b inh 3711 2 ddd decw decrement memory word (m : m + 1) - $0001 t m : m + 1 ind16, x ind16, y ind16, z ext 2701 2711 2721 2731 gggg gggg gggg hh ll 8 8 8 8 ddd ediv extended unsigned integer divide (e : d) / (ix) quotient t ix remainder t d inh 3728 24 dddd edivs extended signed integer divide (e : d) / (ix) quotient t ix remainder t d inh 3729 38 dddd emul extended unsigned multiply (e) * (d) t e : d inh 3725 10 dd d emuls extended signed multiply (e) * (d) t e : d inh 3726 8 dd d eora exclusive or a (a) ? (m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 44 54 64 74 1744 1754 1764 1774 2744 2754 2764 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dd 0 table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 57 eorb exclusive or b (b) ? (m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c4 d4 e4 f4 17c4 17d4 17e4 17f4 27c4 27d4 27e4 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dd 0 eord exclusive or d (d) ? (m : m + 1) t d ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext e, x e, y e, z 84 94 a4 37b4 37c4 37d4 37e4 37f4 2784 2794 27a4 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 6 6 6 dd 0 eore exclusive or e (e) ? (m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3734 3744 3754 3764 3774 jj kk gggg gggg gggg hh ll 4 6 6 6 6 dd 0 fdiv fractional unsigned divide (d) / (ix) t ix remainder t d inh 372b 22 ddd fmuls fractional signed multiply (e) * (d) t e : d [ 31:1 ] 0 t d [ 0 ] inh 3727 8 dddd idiv integer divide (d) / (ix) t ix remainder t d inh 372a 22 d 0 d inc increment memory (m) + $01 t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 03 13 23 1703 1713 1723 1733 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 ddd inca increment a (a) + $01 t a inh 3703 2 ddd incb increment b (b) + $01 t b inh 3713 2 ddd incw increment memory word (m : m + 1) + $0001 t m : m + 1 ind16, x ind16, y ind16, z ext 2703 2713 2723 2733 gggg gggg gggg hh ll 8 8 8 8 ddd jmp jump ea ? t pk : pc ext20 ind20, x ind20, y ind20, z 7a 4b 5b 6b zb hh ll zg gggg zg gggg zg gggg 6 8 8 8 jsr jump to subroutine push (pc) (sk : sp) - $0002 t sk : sp push (ccr) (sk : sp) - $0002 t sk : sp ea ? t pk : pc ext20 ind20, x ind20, y ind20, z fa 89 99 a9 zb hh ll zg gggg zg gggg zg gggg 10 12 12 12 lbcc 2 long branch if carry clear if c = 0, branch rel16 3784 rrrr 6, 4 lbcs 2 long branch if carry set if c = 1, branch rel16 3785 rrrr 6, 4 lbeq 2 long branch if equal to zero if z = 1, branch rel16 3787 rrrr 6, 4 lbev 2 long branch if ev set if ev = 1, branch rel16 3791 rrrr 6, 4 lbge 2 long branch if greater than or equal to zero if n ? v = 0, branch rel16 378c rrrr 6, 4 lbgt 2 long branch if greater than zero if z ; (n ? v) = 0, branch rel16 378e rrrr 6, 4 lbhi 2 long branch if higher if c ; z = 0, branch rel16 3782 rrrr 6, 4 table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 58 mc68hc16s2ts/d lble 2 long branch if less than or equal to zero if z ; (n ? v) = 1, branch rel16 378f rrrr 6, 4 lbls 2 long branch if lower or same if c ; z = 1, branch rel16 3783 rrrr 6, 4 lblt 2 long branch if less than zero if n ? v = 1, branch rel16 378d rrrr 6, 4 lbmi 2 long branch if minus if n = 1, branch rel16 378b rrrr 6, 4 lbmv 2 long branch if mv set if mv = 1, branch rel16 3790 rrrr 6, 4 lbne 2 long branch if not equal to zero if z = 0, branch rel16 3786 rrrr 6, 4 lbpl 2 long branch if plus if n = 0, branch rel16 378a rrrr 6, 4 lbra long branch always if 1 = 1, branch rel16 3780 rrrr 6 lbrn long branch never if 1 = 0, branch rel16 3781 rrrr 6 lbsr long branch to subroutine push (pc) (sk : sp) - 2 t sk : sp push (ccr) (sk : sp) - 2 t sk : sp (pk : pc) + offset t pk : pc rel16 27f9 rrrr 10 lbvc 2 long branch if overflow clear if v = 0, branch rel16 3788 rrrr 6, 4 lbvs 2 long branch if overflow set if v = 1, branch rel16 3789 rrrr 6, 4 ldaa load a (m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 45 55 65 75 1745 1755 1765 1775 2745 2755 2765 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dd 0 ldab load b (m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c5 d5 e5 f5 17c5 17d5 17e5 17f5 27c5 27d5 27e5 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dd 0 d ldd load d (m : m + 1) t d ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext e, x e, y e, z 85 95 a5 37b5 37c5 37d5 37e5 37f5 2785 2795 27a5 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 6 6 6 dd 0 lde load e (m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3735 3745 3755 3765 3775 jj kk gggg gggg gggg hh ll 4 6 6 6 6 dd 0 lded load concatenated e and d (m : m + 1) t e (m + 2 : m + 3) t d ext 2771 hh ll 8 ldhi initialize h and i (m : m + 1) x t h r (m : m + 1) y t i r ext 27b0 8 table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 59 lds load sp (m : m + 1) t sp ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 cf df ef 17cf 17df 17ef 17ff 37bf ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 dd 0 ldx load ix (m : m + 1) t ix ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext cc dc ec 37bc 17cc 17dc 17ec 17fc ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 dd 0 ldy load iy (m : m + 1) t iy ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext cd dd ed 37bd 17cd 17dd 17ed 17fd ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 dd 0 ldz load iz (m : m + 1) t iz ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext ce de ee 37be 17ce 17de 17ee 17fe ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 dd 0 lpstop low power stop if s then stop else nop inh 27f1 4, 20 lsr logical shift right ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 0f 1f 2f 170f 171f 172f 173f ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 0 ddd lsra logical shift right a inh 370f 2 0 ddd lsrb logical shift right b inh 371f 2 0 ddd lsrd logical shift right d inh 27ff 2 0 ddd lsre logical shift right e inh 277f 2 0 ddd lsrw logical shift right word ind16, x ind16, y ind16, z ext 270f 271f 272f 273f gggg gggg gggg hh ll 8 8 8 8 0 ddd mac multiply and accumulate signed 16-bit fractions (hr) * (ir) t e : d (am) + (e : d) t am qualified (ix) t ix qualified (iy) t iy (hr) t iz (m : m + 1) x t hr (m : m + 1) y t ir imm8 7b xoyo 12 d d d table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 60 mc68hc16s2ts/d movb move byte (m 1 ) t m 2 ixp to ext ext to ixp ext to ext 30 32 37fe ff hh ll ff hh ll hh ll hh ll 8 8 10 dd 0 movw move word (m : m + 1 1 ) t m : m + 1 2 ixp to ext ext to ixp ext to ext 31 33 37ff ff hh ll ff hh ll hh ll hh ll 8 8 10 dd 0 mul multiply (a) * (b) t d inh 3724 10 d neg negate memory $00 - (m) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 02 12 22 1702 1712 1722 1732 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 dddd nega negate a $00 - (a) t a inh 3702 2 dddd negb negate b $00 - (b) t b inh 3712 2 dddd negd negate d $0000 - (d) t d inh 27f2 2 dddd nege negate e $0000 - (e) t e inh 2772 2 dddd negw negate memory word $0000 - (m : m + 1) t m : m + 1 ind16, x ind16, y ind16, z ext 2702 2712 2722 2732 gggg gggg gggg hh ll 8 8 8 8 dddd nop null operation inh 274c 2 oraa or a (a) ; (m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 47 57 67 77 1747 1757 1767 1777 2747 2757 2767 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dd 0 orab or b (b) ; (m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c7 d7 e7 f7 17c7 17d7 17e7 17f7 27c7 27d7 27e7 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dd 0 ord or d (d) ; (m : m + 1) t d ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext e, x e, y e, z 87 97 a7 37b7 37c7 37d7 37e7 37f7 2787 2797 27a7 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 6 6 6 dd 0 ore or e (e) ; (m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3737 3747 3757 3767 3777 jj kk gggg gggg gggg hh ll 4 6 6 6 6 dd 0 orp 1 or condition code register (ccr) ; imm16 t ccr imm16 373b jj kk 4 d d d d dddd psha push a (sk : sp) + $0001 t sk : sp push (a) (sk : sp) - $0002 t sk : sp inh 3708 4 table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 61 pshb push b (sk : sp) + $0001 t sk : sp push (b) (sk : sp) - $0002 t sk : sp inh 3718 4 pshm push multiple registers mask bits: 0 = d 1 = e 2 = ix 3 = iy 4 = iz 5 = k 6 = ccr 7 = (reserved) for mask bits 0 to 7: if mask bit set push register (sk : sp) - 2 t sk : sp imm8 34 ii 4 + 2n n = number of iterations pshmac push mac registers mac registers t stack inh 27b8 14 pula pull a (sk : sp) + $0002 t sk : sp pull (a) (sk : sp) ?$0001 t sk : sp inh 3709 6 pulb pull b (sk : sp) + $0002 t sk : sp pull (b) (sk : sp) ?$0001 t sk : sp inh 3719 6 pulm 1 pull multiple registers mask bits: 0 = ccr[15:4] 1 = k 2 = iz 3 = iy 4 = ix 5 = e 6 = d 7 = (reserved) for mask bits 0 to 7: if mask bit set (sk : sp) + 2 t sk : sp pull register imm8 35 ii 4+2(n+1) n = number of iterations d d d d dddd pulmac pull mac state stack t mac registers inh 27b9 16 rmac repeating multiply and accumulate signed 16-bit fractions repeat until (e) < 0 (am) + (h) * (i) t am qualified (ix) t ix; qualified (iy) t iy; (m : m + 1) x t h; (m : m + 1) y t i (e) - 1 t e until (e) < $0000 imm8 fb xoyo 6 + 12 per iteration d d rol rotate left ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 0c 1c 2c 170c 171c 172c 173c ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 dddd rola rotate left a inh 370c 2 dddd rolb rotate left b inh 371c 2 dddd rold rotate left d inh 27fc 2 dddd role rotate left e inh 277c 2 dddd rolw rotate left word ind16, x ind16, y ind16, z ext 270c 271c 272c 273c gggg gggg gggg hh ll 8 8 8 8 dddd table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 62 mc68hc16s2ts/d ror rotate right byte ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 0e 1e 2e 170e 171e 172e 173e ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 dddd rora rotate right a inh 370e 2 dddd rorb rotate right b inh 371e 2 dddd rord rotate right d inh 27fe 2 dddd rore rotate right e inh 277e 2 dddd rorw rotate right word ind16, x ind16, y ind16, z ext 270e 271e 272e 273e gggg gggg gggg hh ll 8 8 8 8 dddd rti 3 return from interrupt (sk : sp) + 2 t sk : sp pull ccr (sk : sp) + 2 t sk : sp pull pc (pk : pc) - 6 t pk : pc inh 2777 12 d d d d dddd rts 4 return from subrou- tine (sk : sp) + 2 t sk : sp pull pk (sk : sp) + 2 t sk : sp pull pc (pk : pc) - 2 t pk : pc inh 27f7 12 sba subtract b from a (a) - (b) t a inh 370a 2 dddd sbca subtract with carry from a (a) - (m) - c t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 42 52 62 72 1742 1752 1762 1772 2742 2752 2762 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dddd sbcb subtract with carry from b (b) - (m) - c t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c2 d2 e2 f2 17c2 17d2 17e2 17f2 27c2 27d2 27e2 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dddd sbcd subtract with carry from d (d) - (m : m + 1) - c t d ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext e, x e, y e, z 82 92 a2 37b2 37c2 37d2 37e2 37f2 2782 2792 27a2 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 6 6 6 dddd table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 63 sbce subtract with carry from e (e) - (m : m + 1) - c t e imm16 ind16, x ind16, y ind16, z ext 3732 3742 3752 3762 3772 jj kk gggg gggg gggg hh ll 4 6 6 6 6 dddd sde subtract d from e (e) - (d) t e inh 2779 2 dddd staa store a (a) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext e, x e, y e, z 4a 5a 6a 174a 175a 176a 177a 274a 275a 276a ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 4 4 4 dd 0 stab store b (b) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext e, x e, y e, z ca da ea 17ca 17da 17ea 17fa 27ca 27da 27ea ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 4 4 4 dd 0 std store d (d) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext e, x e, y e, z 8a 9a aa 37ca 37da 37ea 37fa 278a 279a 27aa ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 6 6 6 dd 0 ste store e (e) t m : m + 1 ind16, x ind16, y ind16, z ext 374a 375a 376a 377a gggg gggg gggg hh ll 6 6 6 6 dd 0 sted store concatenated d and e (e) t m : m + 1 (d) t m + 2 : m + 3 ext 2773 hh ll 8 sts store stack pointer (sp) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8f 9f af 178f 179f 17af 17bf ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 dd 0 stx store ix (ix) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8c 9c ac 178c 179c 17ac 17bc ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 dd 0 sty store iy (iy) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8d 9d ad 178d 179d 17ad 17bd ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 dd 0 table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 64 mc68hc16s2ts/d stz store z (iz) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8e 9e ae 178e 179e 17ae 17be ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 dd 0 suba subtract from a (a) - (m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 40 50 60 70 1740 1750 1760 1770 2740 2750 2760 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dddd subb subtract from b (b) - (m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c0 d0 e0 f0 17c0 17d0 17e0 17f0 27c0 27d0 27e0 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 dddd subd subtract from d (d) - (m : m + 1) t d ind8, x ind8, y ind8, z imm16 ind16, x ind16, y ind16, z ext e, x e, y e, z 80 90 a0 37b0 37c0 37d0 37e0 37f0 2780 2790 27a0 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 4 6 6 6 6 6 6 6 dddd sube subtract from e (e) - (m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3730 3740 3750 3760 3770 jj kk gggg gggg gggg hh ll 4 6 6 6 6 dddd swi software interrupt (pk : pc) + $0002 t pk : pc push (pc) (sk : sp) - $0002 t sk : sp push (ccr) (sk : sp) - $0002 t sk : sp $0 t pk swi vector t pc inh 3720 16 sxt sign extend b into a if b7 = 1 then $ff t a else $00 t a inh 27f8 2 dd tab transfer a to b (a) t b inh 3717 2 dd 0 tap transfer a to ccr (a[7:0]) t ccr[15:8] inh 37fd 4 d d d d dddd tba transfer b to a (b) t a inh 3707 2 dd 0 tbek transfer b to ek (b[3:0]) t ek inh 27fa 2 tbsk transfer b to sk (b[3:0]) t sk inh 379f 2 tbxk transfer b to xk (b[3:0]) t xk inh 379c 2 tbyk transfer b to yk (b[3:0]) t yk inh 379d 2 tbzk transfer b to zk (b[3:0]) t zk inh 379e 2 tde transfer d to e (d) t e inh 277b 2 dd 0 tdmsk transfer d to xmsk : ymsk (d[15:8]) t x mask (d[7:0]) t y mask inh 372f 2 tdp 1 transfer d to ccr (d) t ccr[15:4] inh 372d 4 d d d d dddd ted transfer e to d (e) t d inh 27fb 2 dd 0 table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 65 tedm transfer e and d to am[31:0] sign extend am (e) t am[31:16] (d) t am[15:0] am[35:32] = am31 inh 27b1 4 0 0 tekb transfer ek to b (ek) t b[3:0] $0 t b[7:4] inh 27bb 2 tem transfer e to am[31:16] sign extend am clear am lsb (e) t am[31:16] $00 t am[15:0] am[35:32] = am31 inh 27b2 4 0 0 tmer transfer rounded am to e rounded (am) t temp if (sm (ev ; mv)) then saturation value t e else temp[31:16] t e inh 27b4 6 d ddd tmet transfer truncated am to e if (sm (ev ; mv)) then saturation value t e else am[31:16] t e inh 27b5 2 dd tmxed transfer am to ix : e : d am[35:32] t ix[3:0] am35 t ix[15:4] am[31:16] t e am[15:0] t d inh 27b3 6 tpa transfer ccr to a (ccr[15:8]) t a inh 37fc 2 tpd transfer ccr to d (ccr) t d inh 372c 2 tskb transfer sk to b (sk) t b[3:0] $0 t b[7:4] inh 37af 2 tst test byte zero or minus (m) - $00 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 06 16 26 1706 1716 1726 1736 ff ff ff gggg gggg gggg hh ll 6 6 6 6 6 6 6 dd 00 tsta test a for zero or minus (a) - $00 inh 3706 2 dd 00 tstb test b for zero or minus (b) - $00 inh 3716 2 dd 00 tstd test d for zero or minus (d) - $0000 inh 27f6 2 dd 00 tste test e for zero or minus (e) - $0000 inh 2776 2 dd 00 tstw test for zero or minus word (m : m + 1) - $0000 ind16, x ind16, y ind16, z ext 2706 2716 2726 2736 gggg gggg gggg hh ll 6 6 6 6 dd 00 tsx transfer sp to ix (sk : sp) + $0002 t xk : ix inh 274f 2 tsy transfer sp to iy (sk : sp) + $0002 t yk : iy inh 275f 2 tsz transfer sp to iz (sk : sp) + $0002 t zk : iz inh 276f 2 txkb transfer xk to b (xk) t b[3:0] $0 t b[7:4] inh 37ac 2 txs transfer ix to sp (xk : ix) - $0002 t sk : sp inh 374e 2 txy transfer ix to iy (xk : ix) t yk : iy inh 275c 2 txz transfer ix to iz (xk : ix) t zk : iz inh 276c 2 tykb transfer yk to b (yk) t b[3:0] $0 t b[7:4] inh 37ad 2 tys transfer iy to sp (yk : iy) - $0002 t sk : sp inh 375e 2 tyx transfer iy to ix (yk : iy) t xk : ix inh 274d 2 tyz transfer iy to iz (yk : iy) t zk : iz inh 276d 2 tzkb transfer zk to b (zk) t b[3:0] $0 t b[7:4] inh 37ae 2 tzs transfer iz to sp (zk : iz) - $0002 t sk : sp inh 376e 2 tzx transfer iz to ix (zk : iz) t xk : ix inh 274e 2 tzy transfer iz to iy (zk : iz) t zk : iy inh 275e 2 wai wait for interrupt wait inh 27f3 8 xgab exchange a with b (a) ? (b) inh 371a 2 xgde exchange d with e (d) ? (e) inh 277a 2 xgdx exchange d with ix (d) ? (ix) inh 37cc 2 xgdy exchange d with iy (d) ? (iy) inh 37dc 2 xgdz exchange d with iz (d) ? (iz) inh 37ec 2 table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 66 mc68hc16s2ts/d notes: 1. ccr[15:4] change according to results of operation. the pk field is not affected. 2. cycle times for conditional branches are shown in ?aken, not taken?order. 3. ccr[15:0] change according to copy of ccr pulled from stack. 4. pk field changes according to state pulled from stack. the rest of the ccr is not affected. xgex exchange e with ix (e) ? (ix) inh 374c 2 xgey exchange e with iy (e) ? (iy) inh 375c 2 xgez exchange e with iz (e) ? (iz) inh 376c 2 table 33 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 67 table 34 instruction set abbreviations and symbols a accumulator a x register used in operation am accumulator m m address of one memory byte b accumulator b m + 1 address of byte at m + $0001 ccr condition code register m : m + 1 address of one memory word d accumulator d ( ? )x contents of address pointed to by ix e ?accumulator e ( ... )y contents of address pointed to by iy ek extended addressing extension field ( ... )z contents of address pointed to by iz ir mac multiplicand register e, x ix with e offset hr mac multiplier register e, y iy with e offset ix index register x e, z iz with e offset iy index register y ext extended iz index register z ext20 20-bit extended k address extension register imm8 8-bit immediate pc program counter imm16 16-bit immediate pk program counter extension field ind8, x ix with unsigned 8-bit offset sk stack pointer extension field ind8, y iy with unsigned 8-bit offset sl multiply and accumulate sign latch ind8, z iz with unsigned 8-bit offset sp ? stack pointer ind16, x ix with signed 16-bit offset xk index register x extension field ind16, y iy with signed 16-bit offset yk index register y extension field ind16, z iz with signed 16-bit offset zk index register z extension field ind20, x ix with signed 20-bit offset xmsk modulo addressing index register x mask ind20, y iy with signed 20-bit offset ymsk modulo addressing index register y mask ind20, z iz with signed 20-bit offset s stop disable control bit inh inherent mv am overflow indicator ixp post-modified indexed h half carry indicator rel8 8-bit relative ev am extended overflow indicator rel16 16-bit relative n negative indicator b 4-bit address extension z zero indicator ff 8-bit unsigned offset v two's complement overflow indicator gggg 16-bit signed offset c carry/borrow indicator hh high byte of 16-bit extended address ip interrupt priority field ii 8-bit immediate data sm saturation mode control bit jj high byte of 16-bit immediate data pk program counter extension field kk low byte of 16-bit immediate data bit not affected ll low byte of 16-bit extended address d bit changes as specified mm 8-bit mask 0 bit cleared mmmm 16-bit mask 1 bit set rr 8-bit unsigned relative offset m memory location used in operation rrrr 16-bit signed relative offset r result of operation xo mac index register x offset s source data yo mac index register y offset z 4-bit zero extension + addition and - subtraction or negation (two's complement) ; inclusive or (or) * multiplication ? exclusive or (eor) / division no t complementation > greater : concatenation < less t transferred = equal ? exchanged 3 equal or greater sign bit; also used to show tolerance equal or less sign extension 1 not equal % binary value $ hexadecimal value f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 68 mc68hc16s2ts/d 4.7 exceptions an exception is an event that preempts normal instruction process. exception processing makes the transition from normal instruction execution to execution of a routine that deals with an exception. each exception has an assigned vector that points to an associated handler routine. exception process- ing includes all operations required to transfer control to a handler routine, but does not include execu- tion of the handler routine itself. keep the distinction between exception processing and execution of an exception handler in mind while reading this section. 4.7.1 exception vectors an exception vector is the address of a routine that handles an exception. exception vectors are con- tained in a data structure called the exception vector table, which is located in the first 512 bytes of bank 0. refer to table 35 for the exception vector table. all vectors except the reset vector consist of one word and reside in data space. the reset vector consists of four words that reside in program space. there are 52 predefined or reserved vectors, and 200 user-defined vectors. each vector is assigned an 8-bit number. vector numbers for some exceptions are generated by exter- nal devices; others are supplied by the processor. there is a direct mapping of vector number to vector table address. the processor left shifts the vector number one place (multiplies by two) to convert it to an address. table 35 exception vector table vector number vector address address space type of exception 0 0000 p reset ?initial zk, sk, and pk 0002 p reset ?initial pc 0004 p reset ?initial sp 0006 p reset ?initial iz (direct page) 4 0008 d breakpoint 5 000a d bus error 6 000c d software interrupt 7 000e d illegal instruction 8 0010 d division by zero 9 ?e 0012 ?001c d unassigned, reserved f 001e d uninitialized interrupt 10 0020 d unassigned, reserved 11 0022 d level 1 interrupt autovector 12 0024 d level 2 interrupt autovector 13 0026 d level 3 interrupt autovector 14 0028 d level 4 interrupt autovector 15 002a d level 5 interrupt autovector 16 002c d level 6 interrupt autovector 17 002e d level 7 interrupt autovector 18 0030 d spurious interrupt 19 ?37 0032 ?006e d unassigned, reserved 38 ?ff 0070 ?01fe d user-defined interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 69 4.7.2 exception stack frame during exception processing, the contents of the program counter and condition code register are stacked at a location pointed to by sk:sp. unless it is altered during exception processing, the stacked pk : pc value is the address of the next instruction in the current instruction stream, plus $0006. figure 13 shows the exception stack frame. figure 13 exception stack frame format 4.7.3 exception processing sequence exception processing is performed in four phases. 1. priority of all pending exceptions is evaluated, and the highest priority exception is processed first. 2. processor state is stacked, then the ccr pk extension field is cleared. 3. an exception vector number is acquired and converted to a vector address. 4. the content of the vector address is loaded into the pc, and the processor jumps to the excep- tion handler routine. there are variations within each phase for differing types of exceptions. however, all vectors but the reset vectors contain 16-bit addresses, and the pk field is cleared. exception handlers must be located within bank 0 or vectors must point to a jump table. 4.7.4 types of exceptions exceptions can be either internally or externally generated. external exceptions, which are defined as asynchronous, include interrupts, bus errors (berr), breakpoints (bkpt), and resets (reset). inter- nal exceptions, which are defined as synchronous, include the software interrupt (swi) instruction, the background (bgnd) instruction, illegal instruction exceptions, and the divide-by-zero exception. 4.7.4.1 asynchronous exceptions asynchronous exceptions occur without reference to cpu16 or imb clocks, but exception processing is synchronized. for all asynchronous exceptions but reset, exception processing begins at the first instruction boundary following recognition of an exception. because of pipelining, the stacked return pk : pc value for all asynchronous exceptions, other than re- set, is equal to the address of the next instruction in the current instruction stream plus $0006. the rti instruction, which must terminate all exception handler routines, subtracts $0006 from the stacked value to resume execution of the interrupted instruction stream. 4.7.4.2 synchronous exceptions synchronous exception processing is part of an instruction definition. exception processing for synchro- nous exceptions is always completed, and the first instruction of the handler routine is always executed, before interrupts are detected. ex stack frame condition code register program counter high address high address sp after exception stacking sp before exception stacking f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 70 mc68hc16s2ts/d because of pipelining, the value of pk : pc at the time a synchronous exception executes is equal to the address of the instruction that causes the exception plus $0006. because rti always subtracts $0006 upon return, the stacked pk : pc must be adjusted by the instruction that caused the exception so that execution resumes with the following instruction. for this reason, $0002 is added to the pk : pc value before it is stacked. 4.7.5 multiple exceptions each exception has a hardware priority based upon its relative importance to system operation. asyn- chronous exceptions have higher priorities than synchronous exceptions. exception processing for mul- tiple exceptions is completed by priority, from highest to lowest. priority governs the order in which exception processing occurs, not the order in which exception handlers are executed. unless a bus error, a breakpoint, or a reset occurs during exception processing, the first instruction of all exception handler routines is guaranteed to execute before another exception is processed. because interrupt exceptions have higher priority than synchronous exceptions, the first instruction in an interrupt handler are executed before other interrupts are sensed. bus error, breakpoint, and reset exceptions that occur during exception processing of a previous excep- tion are processed before the first instruction of that exception? handler routine. the converse is not true. if an interrupt occurs during bus error exception processing, for example, the first instruction of the exception handler is executed before interrupts are sensed. this permits the exception handler to mask interrupts during execution. 4.7.6 rti instruction the ?eturn from interrupt instruction?(rti) must be the last instruction in all exception handlers except the reset handler. rti pulls the exception stack frame that was pushed onto the system stack during exception processing, and restores processor state. normal program flow resumes at the address of the instruction that follows the last instruction executed before exception processing began. rti is not used in the reset handler because reset initializes the stack pointer and does not create a stack frame. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 71 5 standby ram module the standby ram module (sram) provides two kbytes of fast ram that is especially useful for system stacks and variable storage. the sram has a dedicated power supply pin so that memory content can be preserved when the mcu is powered down. 5.1 overview the sram module consists of a control register block that is located at a fixed range of addresses in mcu address space, and a 2-kbyte array of two bus cycle static ram that can be mapped to any 2- kbyte boundary in mcu address space. sram control registers are located at addresses $yffb00 yffb08. the module responds to program and data space accesses. data can be read or written in bytes, words, or long words. the ram array must not be mapped so that array addresses overlap module control reg- ister addresses, as overlap makes the registers inaccessible. the sram is powered by v dd in normal operation. during power-down, sram contents are maintained by power from the v stby input. power switching between sources is automatic. table 36 shows the sram address map. 5.2 sram register block there are four sram control registers: the sram module configuration register (rammcr), the sram test register (ramtst), and the sram array base address registers (rambah/rambal). 5.3 sram registers sram responds to both program and data space accesses based on the value in the rasp field in rammcr. this allows code to be executed from ram. use rammcr to determine whether the ram is in stop mode or normal mode. rammcr can deter- mine in which space the array resides and also controls access to the base array registers. reads of unimplemented bits always return zeros. writes do not affect unimplemented bits. notes: 1. y = m111, where m is the logic state of the module mapping (mm) bit in simcr. table 36 sram address map address 15 0 $yffb00 1 ram module configuration register (rammcr) $yffb02 ram test register (ramtst) $yffb04 ram array base address register high (rambah) $yffb06 ram array base address register low (rambal) rammcr ram module configuration register $yffb00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stop 0 0 0 rlck 0 rasp[1:0] not used reset: 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 72 mc68hc16s2ts/d stop ?stop control 0 = ram array operates normally. 1 = ram array enters low-power stop mode. this bit controls whether the ram array is in stop mode or normal operation. reset state is one, leaving the array configured for lpstop operation. in stop mode, the array retains its contents, but cannot be read or written by the cpu. this bit can be read or written at any time. rlck ?ram base address lock 0 = sram base address registers can be written from imb 1 = sram base address registers are locked rlck defaults to zero on reset. it can be written to one once. rasp[1:0] ?ram array space this field limits access to the sram array in microcontrollers that support separate user and supervisor operating modes. because the cpu16 operates in supervisor mode only, rasp1 has no effect. refer to table 37 . ramtst ? ram test register $yffb02 ramtst is for factory test only. reads of this register return zeros and writes have no effect. rambah and rambal specify an sram base address in the system memory map. they can only be written while the sram is in low-power mode (rammcr stop = 1, the default out of reset) and the base address lock is disabled (rammcr rlck = 0, the default out of reset). this prevents accidental remapping of the array. because the cpu16 drives addr[23:20] to the same logic level as addr19, the values of the rambah addr[23:20] fields must match the value of the addr19 field for the array to be accessible. table 37 rasp encoding rasp space x0 program and data x1 program rambah array base address register high $yffb04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used addr 23 addr 22 addr 21 addr 20 addr 19 addr 18 addr 17 addr 16 reset: 0 0 0 0 0 0 0 0 rambal array base address register low $yffb06 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr 15 addr 14 addr 13 addr 12 addr 11 not used reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 73 5.4 sram operation there are five sram operating modes. they include the following: 1. the ram module is in normal mode when powered by v dd . the array can be accessed by byte, word, or long word. a byte or aligned word (high-order byte is at an even address) access only takes one bus cycle or two system clocks. a long word or misaligned word access requires two bus cycles. 2. standby mode is intended to preserve ram contents when v dd is removed. sram contents are maintained by a power source connected to the v stby pin. the standby voltage is referred to as v sb . circuitry within the sram module switches to the higher of v dd or v sb with no loss of data. when sram is powered from the v stby pin, access to the array is not guaranteed. if standby operation is not desired, connect the v stby pin to v ss . 3. reset mode allows the cpu to complete the current bus cycle before resetting. when a syn- chronous reset occurs while a byte or word sram access is in progress, the access is com- pleted. if reset occurs during the first word access of a long-word operation, only the first word access is completed. if reset occurs during the second word access of a long word operation, the entire access is completed. data being read from or written to the ram may be corrupted by asynchronous reset. 4. test mode is used for factory testing of the ram array. 5. writing the stop bit of rammcr causes the sram module to enter stop mode. the ram ar- ray is disabled which, if necessary, allows external logic to decode sram addresses but all data is retained. if v dd falls below v sb , internal circuitry switches to v sb , as in standby mode. exit the stop mode by clearing the stop bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 74 mc68hc16s2ts/d 6 electrical characteristics this section contains 20.97 mhz and 25.17 mhz electrical specification tables and reference timing diagrams. notes: 1. permanent damage can occur if maximum ratings are exceeded. exposure to voltages or currents in excess of recommended values affects device reliability. device modules may not operate normally while being ex- posed to electrical extremes. 2. although sections of the device contain circuitry to protect against damage from high static voltages or elec- trical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. 3. this parameter is periodically sampled rather than 100% tested. 4. all pins except tsc. 5. all functional non-supply pins are internally clamped to v ss for transitions below v ss . all functional pins except extal and xfc are internally clamped to v dd for transitions below v dd . 6. power supply must maintain regulation within operating v dd range during instantaneous and operating max- imum current conditions. 7. total input current for all digital input-only and all digital input/output pins must not exceed 10 ma. exceeding this limit can cause disruption of normal operation. table 38 20.97/25.17 mhz maximum ratings num rating symbol value unit 1 supply voltage 1, 2, 3 v dd ?0.3 to + 6.5 v 2 input voltage 1, 2, 3, 4 v in ?0.3 to + 6.5 v 3 instantaneous maximum current single pin limit (applies to all pins) 1, 3, 5, 6 i d 25 ma 4 operating maximum current digital input disruptive current 5, 6, 7 v ss ?0.3 v in v dd + 0.3 i id ?500 to + 500 m a 5 operating temperature range t a t l to t h ?40 to + 85 c 6 storage temperature range t stg ?55 to + 150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 75 table 39 20.97 mhz typical ratings num rating symbol value unit 1 supply voltage v dd 5.0 v 2 operating temperature t a 25 c 3 v dd supply current run lpstop, vco off lpstop, external clock, max f sys i dd 60 125 3.0 ma m a m a 4 clock synthesizer operating voltage v ddsyn 5.0 v 5 v ddsyn supply current vco on, maximum f sys external clock, maximum f sys lpstop, vco off v dd powered down i ddsyn 1.0 4.5 100 50 ma ma m a m a 6 ram standby voltage v sb 3.0 v 7 ram standby current normal ram operation standby operation i sb 7.0 40 m a m a 8 power dissipation p d 300 mw f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 76 mc68hc16s2ts/d table 40 25.17 mhz typical ratings num rating symbol value unit 1 supply voltage v dd 5.0 v 2 operating temperature t a 25 c 3 v dd supply current run lpstop, vco off lpstop, external clock, max f sys i dd 75 125 3.75 ma m a ma 4 clock synthesizer operating voltage v ddsyn 5.0 v 5 v ddsyn supply current vco on, maximum f sys external clock, maximum f sys lpstop, vco off v dd powered down i ddsyn 1.0 5.0 100 50 ma ma m a m a 6 ram standby voltage v sb 3.0 v 7 ram standby current normal ram operation standby operation i sb 7.0 40 m a m a 8 power dissipation p d 375 mw f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 77 table 41 thermal characteristics num characteristic symbol value unit 1 thermal resistance plastic 100-pin surface mount q ja 42.5 c/w the average chip-junction temperature (t j ) in c can be obtained from: (1) where: t a = ambient temperature, c q ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ?chip internal power p i/o = power dissipation on input and output pins ?user determined for most applications p i/o < p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: (2) solving equations 1 and 2 for k gives: (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . t j t a p d q ja () + = p d kt j 273 c + () ? = kp d t a 273 c + ()q ja p d 2 ++ = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 78 mc68hc16s2ts/d notes: 1. the base configuration of the mc68hc16s2 requires a 32.768 khz reference. 2. all internal registers retain data at 0 hz. 3. assumes that stable v ddsyn is applied, and that the crystal oscillator is stable. lock time is measured from the time v dd and v ddsyn are valid until reset is released. this specification also applies to the period re- quired for pll lock after changing the w and y frequency control bits in the synthesizer control register (syn- cr) while the pll is running, and to the period required for the clock to lock after lpstop. 4. this parameter is periodically sampled rather than 100% tested. 5. assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. total external resistance from the xfc pin due to external leakage must be greater than 15 m w to guarantee this specification. filter network geometry can vary depending upon operating environment. 6. proper layout procedures must be followed to achieve specifications. 7. internal vco frequency (f vco ) is determined by syncr w and y bit values. the syncr x bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. when x = 0, the divider is enabled, and f sys = f vco ? 4. when x = 1, the divider is disabled, and f sys = f vco ? 2. x must equal one when operating at maximum specified f sys . 8. jitter is the average deviation from the programmed frequency measured over the specified interval at max- imum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable ex- ternal clock signal. noise injected into the pll circuitry via v ddsyn and v ss and variation in crystal oscillator frequency increase the j clk percentage for a given interval. when clock jitter is a critical constraint on control system operation, this parameter should be measured during functional testing of the final system. table 42 20.97 mhz clock control timing (v dd and v ddsyn = 5.0 vdc, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit 1 pll reference frequency range 1 f ref 20 50 khz 2 system frequency 2 on-chip pll system frequency range external clock operation f sys dc 4f ref dc 20.97 20.97 20.97 mhz 3 pll lock time 1, 3, 4, 5, 6 t lpll 20 ms 4 vco frequency 7 f vco 2 (f sys max) mhz 5 limp mode clock frequency syncr x bit = 0 syncr x bit = 1 f limp (f sys max)/2 f sys max mhz 6 clkout jitter 1, 4, 5, 6, 8 short term (5 m s interval) long term (500 m s interval) j clk ?1.5 ?0.5 1.0 0.5 % f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 79 notes: 1. refer to notes in table 42 . table 43 25.17 mhz clock control timing (v dd and v ddsyn = 5.0 vdc, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit 1 pll reference frequency range 1 f ref 20 50 khz 2 system frequency 2 on-chip pll system frequency range external clock operation f sys dc 4f ref dc 25.17 25.17 25.17 mhz 3 pll lock time 1, 3, 4, 5, 6 t lpll 20 ms 4 vco frequency 7 f vco 2 (f sys max) mhz 5 limp mode clock frequency syncr x bit = 0 syncr x bit = 1 f limp (f sys max)/2 f sys max mhz 6 clkout jitter 1, 4, 5, 6, 8 short term (5 m s interval) long term (500 m s interval) j clk ?1.5 ?0.5 1.0 0.5 % f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 80 mc68hc16s2ts/d table 44 20.97 mhz dc characteristics (v dd and v ddsyn = 5.0 vdc, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit 1 input high voltage v ih 0.7 (v dd )v dd + 0.3 v 2 input low voltage v il v ss ?0.3 0.2 (v dd )v 3 input hysteresis 1 v hys 0.5 v 4 input leakage current 2 v in = v dd or v ss i in ?.5 2.5 m a 5 high impedance (off-state) leakage current 2 v in = v dd or v ss i oz ?.5 2.5 m a 6 cmos output high voltage 2, 3 i oh = ?0.0 m a v oh v dd ?0.2 v 7 cmos output low voltage 2 i ol = 10.0 m a v ol 0.2 v 8 output high voltage 2, 3 i oh = ?.8 ma v oh v dd ?0.8 v 9 output low voltage 2 i ol = 1.6 ma i ol = 5.3 ma i ol = 12 ma v ol 0.4 0.4 0.4 v 10 three state control input high voltage v ihtsc 1.6 (v dd ) 9.1 v 11 data bus mode select pull-up current 4 v in = v il data[15:0] v in = v ih data[15:0] i msp ?5 ?20 m a 12 v dd supply current 5, 6 run 6 , crystal reference lpstop, crystal reference, vco off (stsim = 0) lpstop, external clock input = max f sys i dd 110 350 5 ma m a ma 13 clock synthesizer operating voltage v ddsyn 4.75 5.25 v 14 v ddsyn supply current 5, 6 vco on, 32.768 khz crystal reference, maximum f sys external clock, maximum f sys lpstop, 32.768 khz crystal reference, vco off (stsim = 0) 32.768 khz, v dd powered down i ddsyn 1 5 100 50 ma ma m a m a 15 ram standby voltage 7 specified v dd applied v dd = v ss v sb 0.0 3.0 5.25 5.25 v 16 ram standby current 7, 6 normal ram operation 8 v dd > v sb ?0.5 v transient condition v sb ?0.5 v 3 v dd 3 v ss + 0.5 v standby operation 7 v dd < v ss + 0.5 v i sb 10 3 50 m a ma m a 17 power dissipation 5, 9 p d 603 mw 18 input capacitance 2, 10 all input-only pins all input/output pins c in 10 20 pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 81 notes: 1. applies to: siz[1:0], as , ds , irq[7:1] , modclk, reset , extal, tsc, bkpt /dsclk, ipipe1/dsi 2. input-only pins: extal, tsc, bkpt /dsclk output-only pins: csboo t , bg /cs1 , clkout, freeze/quot, ipipe0/dso input/output pins: group 1: data[15:0], ipipe1/dsi group 2: port c[6:0] ?addr[22:19]/cs[9:6] , fc[2:0]/cs[5:3] port e[7:0] ?siz[1:0], as , ds , a vec , dsa ck[1:0] port f[7:0] ?rq[7:1] , modclk, addr23/cs10 /eclk, addr[18:0], r/w , berr , br /cs0 , bga ck /cs2 group 3: hal t , reset 3. does not apply to hal t and reset because they are open drain pins. 4. use of an active pulldown device is recommended. 5. total operating current is the sum of the appropriate v dd , supply and v ddsyn supply current. v dd at 3.3v. 6. current measured with system clock frequency of 20.97 mhz, all modules active. 7. the sram module will not switch into standby mode as long as v sb does not exceed v dd by more than 0.5 volts. the sram array cannot be accessed while the module is in standby mode. 8. when v sb is more than 0.3v greater than v dd , current flows between the v stby and v dd pins, which causes standby current to increase toward the maximum transient condition specification. system noise on the v dd and v stby pin can contribute to this condition. 9. power dissipation is measured with a system clock frequency of 20.97 mhz, all modules active. power dissi- pation is calculated using the following expression: p d = maximum v dd (i dd + i ddsyn + i sb ) 10. input capacitance is periodically sampled rather than 100% tested. 19 load capacitance 2 group 1 i/o pins, clkout, freeze/quot, ipipe0 group 2 i/o pins and csboo t , bg /cs group 3 i/o pins group 4 i/o pins c l 90 100 130 200 pf table 44 20.97 mhz dc characteristics (continued) (v dd and v ddsyn = 5.0 vdc, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 82 mc68hc16s2ts/d table 45 25.17 mhz dc characteristics (v dd and v ddsyn = 5.0 vdc, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit 1 input high voltage v ih 0.7 (v dd )v dd + 0.3 v 2 input low voltage v il v ss ?0.3 0.2 (v dd )v 3 input hysteresis 1 v hys 0.5 v 4 input leakage current 2 v in = v dd or v ss i in ?.5 2.5 m a 5 high impedance (off-state) leakage current 2 v in = v dd or v ss i oz ?.5 2.5 m a 6 cmos output high voltage 2, 3 i oh = ?0.0 m a v oh v dd ?0.2 v 7 cmos output low voltage 2 i ol = 10.0 m a v ol 0.2 v 8 output high voltage 2, 3 i oh = ?.8 ma v oh v dd ?0.8 v 9 output low voltage 2 i ol = 1.6 ma i ol = 5.3 ma i ol = 12 ma v ol 0.4 0.4 0.4 v 10 three state control input high voltage v ihtsc 1.6 (v dd ) 9.1 v 11 data bus mode select pull-up current 4 v in = v il data[15:0] v in = v ih data[15:0] i msp ?5 ?20 m a 12 v dd supply current 5, 6 run 6 , crystal reference lpstop, crystal reference, vco off (stsim = 0) lpstop, external clock input = max f sys i dd 140 350 5 ma m a ma 13 clock synthesizer operating voltage v ddsyn 4.75 5.25 v 14 v ddsyn supply current 5, 6 vco on, 32.768 khz crystal reference, maximum f sys external clock, maximum f sys lpstop, 32.768 khz crystal reference, vco off (stsim = 0) 32.768 khz, v dd powered down i ddsyn 2 7 150 100 ma ma m a m a 15 ram standby voltage 7 specified v dd applied v dd = v ss v sb 0.0 3.0 5.25 5.25 v 16 ram standby current 7, 6 normal ram operation 8 v dd > v sb ?0.5 v transient condition v sb ?0.5 v 3 v dd 3 v ss + 0.5 v standby operation 7 v dd < v ss + 0.5 v i sb 10 3 50 m a ma m a 17 power dissipation 5, 9 p d 766 mw 18 input capacitance 2, 10 all input-only pins all input/output pins c in 10 20 pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 83 notes: 1. refer to notes in table 44 . parameters are measured with system clock frequency of 25.17 mhz. 19 load capacitance 2 group 1 i/o pins, clkout, freeze/quot, ipipe0 group 2 i/o pins and csboo t , bg /cs group 3 i/o pins group 4 i/o pins c l 90 100 130 200 pf table 45 25.17 mhz dc characteristics (continued) (v dd and v ddsyn = 5.0 vdc, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 84 mc68hc16s2ts/d table 46 20.97 mhz ac timing (v dd and v ddsyn = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit f1 frequency of operation 2 f sys 4 f ref 20.97 mhz 1 clock period t cyc 47.7 ns 1a eclk period t ecyc 381 ns 1b external clock input period 3 t xcyc 47.7 ns 2, 3 clock pulse width t cw 18.8 ns 2a, 3a eclk pulse width t ecw 183 ns 2b, 3b external clock input high/low time 3 t xchl 23.8 ns 4, 5 clkout rise and fall time t crf ?ns 4a, 5a rise and fall time (all outputs except clkout) t rf ?ns 4b, 5b external clock input rise and fall time 4 t xcrf ?ns 6 clock high to addr, fc, size valid 5 t chav 023ns 7 clock high to addr, data, fc, size high impedance t chazx 047ns 8 clock high to addr, fc, size invalid t chazn 0ns 9 clock low to as , ds , cs asserted 5 t clsa 023ns 9a as to ds or cs asserted (read) 6 t stsa ?0 10 ns 11 addr, fc, size valid to as , cs , (and ds read) asserted t avsa 10 ns 12 clock low to as , ds , cs negated t clsn 223ns 13 as , ds , cs negated to addr, fc size invalid (address hold) t snai 10 ns 14 as , cs (and ds read) width asserted t swa 80 ns 14a ds , cs width asserted (write) t swaw 36 ns 14b as , cs (and ds read) width asserted (fast cycle) t swdw 32 ns 15 as , ds , cs width negated 7 t sn 32 ns 16 clock high to as , ds , r/w high impedance t chsz ?7ns 17 as , ds , cs negated to r/w high t snrn 10 ns 18 clock high to r/w high t chrh 023ns 20 clock high to r/w low t chrl 023ns 21 r/w high to as , cs asserted t raaa 10 ns 22 r/w low to ds , cs asserted (write) t rasa 54 ns 23 clock high to data out valid t chdo ?3ns 24 data out valid to negating edge of as , cs (fast write cycle) t dvasn 10 ns 25 ds , cs negated to data out invalid (data out hold) t sndoi 10 ns 26 data out valid to ds , cs asserted (write) t dvsa 10 ns 27 data in valid to clock low (data setup) 5 t dicl 5ns 27a late berr , hal t asserted to clock low (setup time) t belcl 15 ns 28 as , ds negated to dsa ck[1:0] , berr , hal t , a vec negated t sndn 060ns 29 ds , cs negated to data in invalid (data in hold) 8 t sndi 0ns 29a ds , cs negated to data in high impedance 8, 9 t shdi ?8ns 30 clkout low to data in invalid (fast cycle hold) 8 t cldi 10 ns 30a clkout low to data in high impedance 8 t cldh ?2ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 85 31 dsa ck[1:0] asserted to data in valid 10 t dadi ?6ns 33 clock low to bg asserted/negated t clban ?3ns 35 br asserted to bg asserted 11 t braga 1t cyc 37 bga ck asserted to bg negated t gagn 12t cyc 39 bg width negated t gh 2t cyc 39a bg width asserted t ga 1t cyc 46 r/w width asserted (write or read) t rwa 115 ns 46a r/w width asserted (fast write or read cycle) t rwas 70 ns 47a asynchronous input setup time br , bga ck , dsa ck[1:0] , berr , a vec , hal t t aist 5ns 47b asynchronous input hold time t aiht 12 ns 48 dsa ck[1:0] asserted to berr , hal t asserted 12 t daba ?0ns 53 data out hold from clock high t doch 0ns 54 clock high to data out high impedance t chdh ?3ns 55 r/w asserted to data bus impedance change t radc 32 ns 70 clock low to data bus driven (show cycle) t scldd 023ns 71 data setup time to clock low (show cycle) t sclds 10 ns 72 data hold from clock low (show cycle) t scldh 10 ns 73 bkpt input setup time t bkst 10 ns 74 bkpt input hold time t bkht 10 ns 75 mode select setup time (data[15:0], modclk, bkpt )t mss 20 t cyc 76 mode select hold time (data[15:0], modclk, bkpt) t msh 0ns 77 reset assertion time 13 t rsta 4t cyc 78 reset rise time 14, 15 t rstr ?0t cyc 100 clkout high to phase 1 asserted 16 t chp1a 340ns 101 clkout high to phase 2 asserted t chp2a 340ns 102 phase 1 valid to as or ds asserted t p1vsa 10 ns 103 phase 2 valid to as or ds asserted t p2vsn 10 ns 104 as or ds valid to phase 1 negated t sap1n 10 ns 105 as or ds valid to phase 2 negated t snp2n 10 ns table 46 20.97 mhz ac timing (continued) (v dd and v ddsyn = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 86 mc68hc16s2ts/d notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. the base configuration of the mc68hc16s2 requires a 32.768 khz crystal reference. 3. when an external clock is used, minimum high and low times are based on a 50% duty cycle. the minimum allowable t xcyc period is reduced when the duty cycle of the external clock varies. the relationship between ex- ternal clock input duty cycle and minimum t xcyc is expressed: minimum t xcyc period = minimum t xchl / (50% ?external clock input duty cycle tolerance). 4. parameters for an external clock signal applied while the internal pll is disabled (modclk pin held low during reset). does not pertain to an external reference applied while the pll is enabled (modclk pin held high during reset). when the pll is enabled, the clock synthesizer detects successive transitions of the reference signal. if transitions occur within the correct clock period, rise/fall times and duty cycle are not critical. 5. address access time = (2.5 + ws) t cyc ?t chav ?t dicl chip-select access time = (2 + ws) t cyc ?t clsa ?t dicl where: ws = number of wait states. when fast termination is used (2 clock bus) ws = ?. 6. specification 9a is the worst-case skew between as and ds or cs . the amount of skew depends on the relative loading of these signals. when loads are kept within specified limits, skew will not cause as and ds to fall out- side the limits shown in specification 9. 7. if multiple chip selects are used, cs width negated (specification 15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. the cs width negated specification between multiple chip selects does not apply to chip selects being used for synchronous eclk cycles. 8. hold times are specified with respect to ds or cs on asynchronous reads and with respect to clkout on fast cycle reads. the user is free to use either hold time. 9. maximum value is equal to (t cyc / 2) + 25 ns. 10. if the asynchronous setup time (specification 47a) requirements are satisfied, the dsa ck[1:0] low to data setup time (specification 31) and dsa ck[1:0] low to berr low setup time (specification 48) can be ignored. the data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. berr must satisfy only the late berr low to clock low setup time (specification 27a) for the following clock cycle. 11. to ensure coherency during every operand transfer, bg is not asserted in response to br until after all cycles of the current operand transfer are complete. 12. in the absence of dsa ck[1:0] , berr is an asynchronous input using the asynchronous setup time (specification 47a). 13. after external reset negation is detected, a short transition period (approximately 2 t cyc ) elapses, then the sim drives reset low for 512 tcyc. 14. external assertion of the reset input can overlap internally-generated resets. to ensure that an external reset is recognized in all cases, reset must be asserted for at least 590 clkout cycles. 15. external logic must pull reset high during this period in order for normal mcu operation to begin. 16. eight pipeline states are multiplexed into ipipe[1:0]. the multiplexed signals have two phases. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 87 table 47 25.17 mhz ac timing (v dd and v ddsyn = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit f1 frequency of operation 2 f sys 4 f ref 25.166 mhz 1 clock period t cyc 39.7 ns 1a eclk period t ecyc 318 ns 1b external clock input period 3 t xcyc 39.7 ns 2, 3 clock pulse width t cw 15 ns 2a, 3a eclk pulse width t ecw 155 ns 2b, 3b external clock input high/low time 3 t xchl 19.8 ns 4, 5 clkout rise and fall time t crf ?ns 4a, 5a rise and fall time (all outputs except clkout) t rf ?ns 4b, 5b external clock input rise and fall time 4 t xcrf ?ns 6 clock high to addr, fc, size valid 5 t chav 019ns 7 clock high to addr, data, fc, size high impedance t chazx 039ns 8 clock high to addr, fc, size invalid t chazn 0ns 9 clock low to as , ds , cs asserted 5 t clsa 219ns 9a as to ds or cs asserted (read) 6 t stsa ?0 15 ns 11 addr, fc, size valid to as , cs , (and ds read) asserted t avsa 8ns 12 clock low to as , ds , cs negated t clsn 219ns 13 as , ds , cs negated to addr, fc size invalid (address hold) t snai 8ns 14 as , cs (and ds read) width asserted t swa 65 ns 14a ds , cs width asserted (write) t swaw 25 ns 14b as , cs (and ds read) width asserted (fast cycle) t swdw 22 ns 15 as , ds , cs width negated 7 t sn 22 ns 16 clock high to as , ds , r/w high impedance t chsz ?9ns 17 as , ds , cs negated to r/w high t snrn 10 ns 18 clock high to r/w high t chrh 019ns 20 clock high to r/w low t chrl 019ns 21 r/w high to as , cs asserted t raaa 10 ns 22 r/w low to ds , cs asserted (write) t rasa 40 ns 23 clock high to data out valid t chdo ?9ns 24 data out valid to negating edge of as , cs (fast write cycle) t dvasn 7ns 25 ds , cs negated to data out invalid (data out hold) t sndoi 5ns 26 data out valid to ds , cs asserted (write) t dvsa 8ns 27 data in valid to clock low (data setup) 5 t dicl 5ns 27a late berr , hal t asserted to clock low (setup time) t belcl 10 ns 28 as , ds negated to dsa ck[1:0] , berr , hal t , a vec negated t sndn 050ns 29 ds , cs negated to data in invalid (data in hold) 8 t sndi 0ns 29a ds , cs negated to data in high impedance 8, 9 t shdi ?5ns 30 clkout low to data in invalid (fast cycle hold) 8 t cldi 8ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 88 mc68hc16s2ts/d notes: 1. refer to notes in table 46 . parameters are measured with system clock frequency of 25.17 mhz. 30a clkout low to data in high impedance 8 t cldh ?0ns 31 dsa ck[1:0] asserted to data in valid 10 t dadi ?5ns 33 clock low to bg asserted/negated t clban ?9ns 35 br asserted to bg asserted 11 t braga 1t cyc 37 bga ck asserted to bg negated t gagn 12t cyc 39 bg width negated t gh 2t cyc 39a bg width asserted t ga 1t cyc 46 r/w width asserted (write or read) t rwa 90 ns 46a r/w width asserted (fast write or read cycle) t rwas 55 ns 47a asynchronous input setup time br , bga ck , dsa ck[1:0] , berr , a vec , hal t t aist 5ns 47b asynchronous input hold time t aiht 10 ns 48 dsa ck[1:0] asserted to berr , hal t asserted 12 t daba ?7ns 53 data out hold from clock high t doch 0ns 54 clock high to data out high impedance t chdh ?3ns 55 r/w asserted to data bus impedance change t radc 25 ns 70 clock low to data bus driven (show cycle) t scldd 019ns 71 data setup time to clock low (show cycle) t sclds 8ns 72 data hold from clock low (show cycle) t scldh 8ns 73 bkpt input setup time t bkst 10 ns 74 bkpt input hold time t bkht 10 ns 75 mode select setup time (data[15:0], modclk, bkpt )t mss 20 t cyc 76 mode select hold time (data[15:0], modclk, bkpt) t msh 0ns 77 reset assertion time 13 t rsta 4t cyc 78 reset rise time 14, 15 t rstr ?0t cyc 100 clkout high to phase 1 asserted 16 t chp1a 334ns 101 clkout high to phase 2 asserted t chp2a 334ns 102 phase 1 valid to as or ds asserted t p1vsa 9ns 103 phase 2 valid to as or ds asserted t p2vsn 9ns 104 as or ds valid to phase 1 negated t sap1n 9ns 105 as or ds valid to phase 2 negated t snp2n 9ns table 47 25.17 mhz ac timing (continued) (v dd and v ddsyn = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 89 figure 14 clkout output timing diagram figure 15 external clock input timing diagram figure 16 eclk output timing diagram 16 clkout tim 4 clkout 5 2 3 1 16 ext clk input tim 4b extal 5b 2b 3b 1b note: timing shown with respect to 20% and 70% v dd . pulse width shown with respect to 50% v dd . 16 eclk output tim 4a eclk 5a 2a 3a 1a note: timing shown with respect to 20% and 70% v dd. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 90 mc68hc16s2ts/d figure 17 read cycle timing diagram 16 rd cyc tim clkout s0 s1 s2 s3 s4 s5 103 105 47b 47a 102 100 101 104 48 27a 27 29a 28 20 31 29 47a 46 18 21 9a 9 11 12 13 15 8 6 addr[23:0] fc[2:0] siz[1:0] ds cs r/w as dsack0 dsack1 data[15:0] berr halt bkpt asynchronous inputs ipipe0 ipipe1 phase 1 phase 2 14 17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 91 figure 18 write cycle timing diagram 16 wr cyc tim clkout s0 s1 s2 s3 s4 s5 48 27a 28 17 25 20 9 11 14 12 13 15 8 6 addr[23:20] fc[2:0] siz[1:0] ds cs r/w as dsack0 dsack1 data[15:0] berr halt bkpt 54 53 55 47a 46 26 23 9 74 73 103 105 102 100 101 104 ipipe0 ipipe1 phase 1 phase 2 22 14a 21 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 92 mc68hc16s2ts/d figure 19 fast termination read cycle timing diagram clkout s0 s1 s4 s5 s0 18 9 6 addr[23:0] fc[2:0] siz[1:0] ds cs r/w as data[15:0] 8 bkpt 12 46a 30 29a 20 74 30a 29 phase 1 phase 2 100 102 104 103 105 101 ipipe0 ipipe1 27 73 14b 16 fast rd cyc tim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 93 figure 20 fast termination write cycle timing diagram clkout s0 s1 s4 s5 s0 20 9 6 addr[23:0] fc[1:0] siz[1:0] ds cs r/w as data[15:0] 14b 8 bkpt 100 101 ipipe0 ipipe1 phase 1 12 46a 23 73 phase 2 24 18 25 16 fast wr cyc tim 105 102 104 103 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 94 mc68hc16s2ts/d figure 21 bus arbitration timing diagram ?active bus case 16 bus arb tim clkout s0 s1 s2 s3 s4 addr[23:0] data[15:0] 7 s98 a5 a5 a2 47a 39a 35 33 33 16 s5 as ds r/w dsack0 dsack1 br bg bgack 37 phase 1 phase 2 100 102 104 103 105 101 ipipe0 ipipe1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 95 figure 22 bus arbitration timing diagram ?idle bus case 16 bus arb tim idle clkout a0 a5 addr[23:0] data[15:0] a2 a3 a0 a5 br as bg bgack 47a 33 33 47a 37 47a 35 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 96 mc68hc16s2ts/d figure 23 show cycle timing diagram clkout s0 s41 s42 s0 s1 s2 6 addr[23:0] r/w as 8 ds 72 data[15:0] bkpt 71 70 12 9 15 18 20 show cycle start of external cycle 74 s43 16 shw cyc tim phase 1 phase 2 phase 1 phase 2 100 102 104 103 105 101 73 ipipe0 ipipe1 note: show cycles can stretch during clock phase s42 when bus accesses take longer than two cycles due to imb module wait-state insertion. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 97 figure 24 chip-select timing diagram figure 25 reset and mode select timing diagram 16 chip sel tim 6 6 8 11 11 25 53 54 23 55 29a 29 27 46 46 14a 12 13 15 9 9 12 14 9 18 20 18 s0 s1 s2 s3 s4 s5 s0 s1 s2 s3 s4 s5 14 clkout addr[23:0] fc[2:0] siz[1:0] as ds cs r/w data[15:0] 21 17 17 16 rst/mode sel tim reset data[15:0], 75 76 77 78 modclk, bkpt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 98 mc68hc16s2ts/d notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. table 48 20.97 mhz background debugging mode timing (v dd and v ddsyn = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit b0 dsi input setup time t dsisu 15 ns b1 dsi input hold time t dsih 10 ns b2 dsclk setup time t dscsu 15 ns b3 dsclk hold time t dsch 10 ns b4 dso delay time t dsod ?5ns b5 dsclk cycle time t dsccyc 2t cyc b6 clkout high to freeze asserted/negated t frzan ?0ns b7 clkout high to ipipe1 high impedance t ifz ?0ns b8 clkout high to ipipe1 valid t if ?0ns b9 dsclk low time t dsclo 1t cyc b10 ipipe1 high impedance to freeze asserted t ipfa tbd t cyc b11 freeze negated to ipipe[1:0] active t frip tbd t cyc table 49 25.17 mhz background debugging mode timing (v dd and v ddsyn = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit b0 dsi input setup time t dsisu 10 ns b1 dsi input hold time t dsih 5ns b2 dsclk setup time t dscsu 10 ns b3 dsclk hold time t dsch 5ns b4 dso delay time t dsod ?0ns b5 dsclk cycle time t dsccyc 2t cyc b6 clkout high to freeze asserted/negated t frzan ?0ns b7 clkout high to ipipe1 high impedance t ifz ?0ns b8 clkout high to ipipe1 valid t if ?0ns b9 dsclk low time t dsclo 1t cyc b10 ipipe1 high impedance to freeze asserted t ipfa tbd t cyc b11 freeze negated to ipipe[1:0] active t frip tbd t cyc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 99 figure 26 background debugging mode timing diagram ? serial communication figure 27 background debugging mode timing diagram ? freeze assertion 16 bdm ser com tim b1 b3 b2 b0 b4 clkout freeze bkpt /dsclk ipipe1/dsi ipipe0/dso b5 b9 16 bdm frz tim b8 clkout freeze ipipe1/dsi b6 b7 b11 b6 b10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 100 mc68hc16s2ts/d notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. when previous bus cycle is not an eclk cycle, the address may be valid before eclk goes low. 3. address access time = t ecyc ?t ead ?t edsr . 4. chip select access time = t ecyc ?t ecsd ?t edsr . table 50 20.97 mhz eclk bus timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit e1 eclk low to address valid 2 t ead ?8ns e2 eclk low to address hold t eah 10 ns e3 eclk low to cs valid (cs delay) t ecsd 120 ns e4 eclk low to cs hold t ecsh 10 ns e5 cs negated width t ecsn 25 ns e6 read data setup time t edsr 25 ns e7 read data hold time t edhr 5ns e8 eclk low to data high impedance t edhz ?8ns e9 cs negated to data hold (read) t ecdh 0ns e10 cs negated to data high impedance t ecdz ?t cyc e11 eclk low to data valid (write) t eddw ?t cyc e12 eclk low to data hold (write) t edhw 10 ns e13 address access time (read) 3 t eacc 308 ns e14 chip-select access time (read) 4 t eacs 236 ns e15 address setup time t eas 1/2 t cyc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 101 notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. when previous bus cycle is not an eclk cycle, the address may be valid before eclk goes low. 3. address access time = t ecyc ?t ead ?t edsr . 4. chip select access time = t ecyc ?t ecsd ?t edsr . table 51 25.17 mhz eclk bus timing (v dd and v ddsyn = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit e1 eclk low to address valid 2 t ead ?0ns e2 eclk low to address hold t eah 10 ns e3 eclk low to cs valid (cs delay) t ecsd 100 ns e4 eclk low to cs hold t ecsh 10 ns e5 cs negated width t ecsn 20 ns e6 read data setup time t edsr 25 ns e7 read data hold time t edhr 5ns e8 eclk low to data high impedance t edhz ?0ns e9 cs negated to data hold (read) t ecdh 0ns e10 cs negated to data high impedance t ecdz ?t cyc e11 eclk low to data valid (write) t eddw ?t cyc e12 eclk low to data hold (write) t edhw 5ns e13 address access time (read) 3 t eacc 255 ns e14 chip-select access time (read) 4 t eacs 195 ns e15 address setup time t eas 1/2 t cyc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mc68hc16s2 102 mc68hc16s2ts/d figure 28 eclk timing diagram hc16 e cycle tim clkout addr[23:0] cs eclk data[15:0] e1 2a 3a e2 e5 e4 e3 e9 e7 e8 e10 e12 e14 e13 1a data[15:0] e15 e11 write read write e6 r/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2 motorola mc68hc16s2ts/d 103 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc16s2ts/d how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. 1-800-441-2447 or 602/303-5454 mfax: rmfax0@email.sps.mot.com - touchtone (602) 244-6609 internet: http://design-net.com japan: nippon motorola ltd.; tatsumi-spd-jldc, 6f seibu-butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan. 03-3521-8315 asia pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. mcuinit, mcuasm, mcudebug, and rtek are trademarks of motorola, inc. motorola and the motorola logo are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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